diff options
| -rw-r--r-- | lib/Target/AArch64/AArch64ISelLowering.cpp | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/lib/Target/AArch64/AArch64ISelLowering.cpp b/lib/Target/AArch64/AArch64ISelLowering.cpp index 7311d554ee..15232523fe 100644 --- a/lib/Target/AArch64/AArch64ISelLowering.cpp +++ b/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -4241,8 +4241,8 @@ AArch64TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, // Test if V1 is a CONCAT_VECTORS. if (V1.getOpcode() == ISD::CONCAT_VECTORS) { if (V1.getOperand(1).getOpcode() == ISD::UNDEF) { - int V1EltNum = V1.getOperand(0).getValueType().getVectorNumElements(); - assert((Lane < V1EltNum) && "Invalid vector lane access"); + assert((Lane < V1.getOperand(0).getValueType().getVectorNumElements()) + && "Invalid vector lane access"); return DAG.getNode(AArch64ISD::NEON_VDUPLANE, dl, VT, V1.getOperand(0), DAG.getConstant(Lane, MVT::i64)); } |