From 1e06bcbd633175d75d13aaa5695ca0633ba86068 Mon Sep 17 00:00:00 2001 From: Venkatraman Govindaraju Date: Tue, 4 Jun 2013 18:33:25 +0000 Subject: Sparc: No functionality change. Cleanup whitespaces, comment formatting etc., git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183243 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Sparc/DelaySlotFiller.cpp | 74 ++++++++++++++++----------------- lib/Target/Sparc/FPMover.cpp | 10 ++--- lib/Target/Sparc/LLVMBuild.txt | 3 +- lib/Target/Sparc/README.txt | 6 +-- lib/Target/Sparc/Sparc.h | 4 +- lib/Target/Sparc/Sparc.td | 2 +- lib/Target/Sparc/SparcAsmPrinter.cpp | 22 +++++----- lib/Target/Sparc/SparcCallingConv.td | 2 +- lib/Target/Sparc/SparcFrameLowering.cpp | 8 ++-- lib/Target/Sparc/SparcFrameLowering.h | 4 +- lib/Target/Sparc/SparcISelLowering.cpp | 43 +++++++++---------- lib/Target/Sparc/SparcInstrFormats.td | 9 ++-- lib/Target/Sparc/SparcInstrInfo.cpp | 16 +++---- lib/Target/Sparc/SparcInstrInfo.h | 6 +-- lib/Target/Sparc/SparcInstrInfo.td | 48 ++++++++++----------- lib/Target/Sparc/SparcRegisterInfo.cpp | 8 ++-- lib/Target/Sparc/SparcRegisterInfo.td | 36 ++++++++-------- lib/Target/Sparc/SparcSubtarget.cpp | 2 +- lib/Target/Sparc/SparcSubtarget.h | 8 ++-- 19 files changed, 157 insertions(+), 154 deletions(-) diff --git a/lib/Target/Sparc/DelaySlotFiller.cpp b/lib/Target/Sparc/DelaySlotFiller.cpp index 271c630e39..5ec54a6a84 100644 --- a/lib/Target/Sparc/DelaySlotFiller.cpp +++ b/lib/Target/Sparc/DelaySlotFiller.cpp @@ -42,7 +42,7 @@ namespace { const TargetInstrInfo *TII; static char ID; - Filler(TargetMachine &tm) + Filler(TargetMachine &tm) : MachineFunctionPass(ID), TM(tm), TII(tm.getInstrInfo()) { } virtual const char *getPassName() const { @@ -107,7 +107,7 @@ bool Filler::runOnMachineBasicBlock(MachineBasicBlock &MBB) { MachineBasicBlock::iterator MI = I; ++I; - //If MI is restore, try combining it with previous inst. + // If MI is restore, try combining it with previous inst. if (!DisableDelaySlotFiller && (MI->getOpcode() == SP::RESTORErr || MI->getOpcode() == SP::RESTOREri)) { @@ -115,7 +115,7 @@ bool Filler::runOnMachineBasicBlock(MachineBasicBlock &MBB) { continue; } - //If MI has no delay slot, skip + // If MI has no delay slot, skip. if (!MI->hasDelaySlot()) continue; @@ -135,7 +135,7 @@ bool Filler::runOnMachineBasicBlock(MachineBasicBlock &MBB) { unsigned structSize = 0; if (needsUnimp(MI, structSize)) { MachineBasicBlock::iterator J = MI; - ++J; //skip the delay filler. + ++J; // skip the delay filler. assert (J != MBB.end() && "MI needs a delay instruction."); BuildMI(MBB, ++J, I->getDebugLoc(), TII->get(SP::UNIMP)).addImm(structSize); @@ -165,13 +165,13 @@ Filler::findDelayInstr(MachineBasicBlock &MBB, if (J->getOpcode() == SP::RESTORErr || J->getOpcode() == SP::RESTOREri) { - //change retl to ret + // change retl to ret. slot->setDesc(TII->get(SP::RET)); return J; } } - //Call's delay filler can def some of call's uses. + // Call's delay filler can def some of call's uses. if (slot->isCall()) insertCallDefsUses(slot, RegDefs, RegUses); else @@ -241,12 +241,12 @@ bool Filler::delayHasHazard(MachineBasicBlock::iterator candidate, unsigned Reg = MO.getReg(); if (MO.isDef()) { - //check whether Reg is defined or used before delay slot. + // check whether Reg is defined or used before delay slot. if (IsRegInSet(RegDefs, Reg) || IsRegInSet(RegUses, Reg)) return true; } if (MO.isUse()) { - //check whether Reg is defined before delay slot. + // check whether Reg is defined before delay slot. if (IsRegInSet(RegDefs, Reg)) return true; } @@ -259,7 +259,7 @@ void Filler::insertCallDefsUses(MachineBasicBlock::iterator MI, SmallSet& RegDefs, SmallSet& RegUses) { - //Call defines o7, which is visible to the instruction in delay slot. + // Call defines o7, which is visible to the instruction in delay slot. RegDefs.insert(SP::O7); switch(MI->getOpcode()) { @@ -283,7 +283,7 @@ void Filler::insertCallDefsUses(MachineBasicBlock::iterator MI, } } -//Insert Defs and Uses of MI into the sets RegDefs and RegUses. +// Insert Defs and Uses of MI into the sets RegDefs and RegUses. void Filler::insertDefsUses(MachineBasicBlock::iterator MI, SmallSet& RegDefs, SmallSet& RegUses) @@ -299,8 +299,8 @@ void Filler::insertDefsUses(MachineBasicBlock::iterator MI, if (MO.isDef()) RegDefs.insert(Reg); if (MO.isUse()) { - //Implicit register uses of retl are return values and - //retl does not use them. + // Implicit register uses of retl are return values and + // retl does not use them. if (MO.isImplicit() && MI->getOpcode() == SP::RETL) continue; RegUses.insert(Reg); @@ -308,7 +308,7 @@ void Filler::insertDefsUses(MachineBasicBlock::iterator MI, } } -//returns true if the Reg or its alias is in the RegSet. +// returns true if the Reg or its alias is in the RegSet. bool Filler::IsRegInSet(SmallSet& RegSet, unsigned Reg) { // Check Reg and all aliased Registers. @@ -355,24 +355,24 @@ static bool combineRestoreADD(MachineBasicBlock::iterator RestoreMI, MachineBasicBlock::iterator AddMI, const TargetInstrInfo *TII) { - //Before: add , , %i[0-7] - // restore %g0, %g0, %i[0-7] + // Before: add , , %i[0-7] + // restore %g0, %g0, %i[0-7] // - //After : restore , , %o[0-7] + // After : restore , , %o[0-7] unsigned reg = AddMI->getOperand(0).getReg(); if (reg < SP::I0 || reg > SP::I7) return false; - //Erase RESTORE + // Erase RESTORE. RestoreMI->eraseFromParent(); - //Change ADD to RESTORE + // Change ADD to RESTORE. AddMI->setDesc(TII->get((AddMI->getOpcode() == SP::ADDrr) ? SP::RESTORErr : SP::RESTOREri)); - //map the destination register + // Map the destination register. AddMI->getOperand(0).setReg(reg - SP::I0 + SP::O0); return true; @@ -382,17 +382,17 @@ static bool combineRestoreOR(MachineBasicBlock::iterator RestoreMI, MachineBasicBlock::iterator OrMI, const TargetInstrInfo *TII) { - //Before: or , , %i[0-7] - // restore %g0, %g0, %i[0-7] - // and or is zero, + // Before: or , , %i[0-7] + // restore %g0, %g0, %i[0-7] + // and or is zero, // - //After : restore , , %o[0-7] + // After : restore , , %o[0-7] unsigned reg = OrMI->getOperand(0).getReg(); if (reg < SP::I0 || reg > SP::I7) return false; - //check whether it is a copy + // check whether it is a copy. if (OrMI->getOpcode() == SP::ORrr && OrMI->getOperand(1).getReg() != SP::G0 && OrMI->getOperand(2).getReg() != SP::G0) @@ -403,15 +403,15 @@ static bool combineRestoreOR(MachineBasicBlock::iterator RestoreMI, && (!OrMI->getOperand(2).isImm() || OrMI->getOperand(2).getImm() != 0)) return false; - //Erase RESTORE + // Erase RESTORE. RestoreMI->eraseFromParent(); - //Change OR to RESTORE + // Change OR to RESTORE. OrMI->setDesc(TII->get((OrMI->getOpcode() == SP::ORrr) ? SP::RESTORErr : SP::RESTOREri)); - //map the destination register + // Map the destination register. OrMI->getOperand(0).setReg(reg - SP::I0 + SP::O0); return true; @@ -421,10 +421,10 @@ static bool combineRestoreSETHIi(MachineBasicBlock::iterator RestoreMI, MachineBasicBlock::iterator SetHiMI, const TargetInstrInfo *TII) { - //Before: sethi imm3, %i[0-7] - // restore %g0, %g0, %g0 + // Before: sethi imm3, %i[0-7] + // restore %g0, %g0, %g0 // - //After : restore %g0, (imm3<<10), %o[0-7] + // After : restore %g0, (imm3<<10), %o[0-7] unsigned reg = SetHiMI->getOperand(0).getReg(); if (reg < SP::I0 || reg > SP::I7) @@ -435,11 +435,11 @@ static bool combineRestoreSETHIi(MachineBasicBlock::iterator RestoreMI, int64_t imm = SetHiMI->getOperand(1).getImm(); - //is it a 3 bit immediate? + // Is it a 3 bit immediate? if (!isInt<3>(imm)) return false; - //make it a 13 bit immediate + // Make it a 13 bit immediate. imm = (imm << 10) & 0x1FFF; assert(RestoreMI->getOpcode() == SP::RESTORErr); @@ -451,7 +451,7 @@ static bool combineRestoreSETHIi(MachineBasicBlock::iterator RestoreMI, RestoreMI->getOperand(2).ChangeToImmediate(imm); - //Erase the original SETHI + // Erase the original SETHI. SetHiMI->eraseFromParent(); return true; @@ -460,11 +460,11 @@ static bool combineRestoreSETHIi(MachineBasicBlock::iterator RestoreMI, bool Filler::tryCombineRestoreWithPrevInst(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) { - //No previous instruction + // No previous instruction. if (MBBI == MBB.begin()) return false; - //asssert that MBBI is "restore %g0, %g0, %g0" + // assert that MBBI is a "restore %g0, %g0, %g0". assert(MBBI->getOpcode() == SP::RESTORErr && MBBI->getOperand(0).getReg() == SP::G0 && MBBI->getOperand(1).getReg() == SP::G0 @@ -472,7 +472,7 @@ bool Filler::tryCombineRestoreWithPrevInst(MachineBasicBlock &MBB, MachineBasicBlock::iterator PrevInst = MBBI; --PrevInst; - //Cannot combine with a delay filler + // It cannot combine with a delay filler. if (isDelayFiller(MBB, PrevInst)) return false; @@ -484,6 +484,6 @@ bool Filler::tryCombineRestoreWithPrevInst(MachineBasicBlock &MBB, case SP::ORri: return combineRestoreOR(MBBI, PrevInst, TII); break; case SP::SETHIi: return combineRestoreSETHIi(MBBI, PrevInst, TII); break; } - //Cannot combine with the previous instruction + // It cannot combine with the previous instruction. return false; } diff --git a/lib/Target/Sparc/FPMover.cpp b/lib/Target/Sparc/FPMover.cpp index 1325b98cf0..5592668952 100644 --- a/lib/Target/Sparc/FPMover.cpp +++ b/lib/Target/Sparc/FPMover.cpp @@ -33,9 +33,9 @@ namespace { /// layout, etc. /// TargetMachine &TM; - + static char ID; - explicit FPMover(TargetMachine &tm) + explicit FPMover(TargetMachine &tm) : MachineFunctionPass(ID), TM(tm) { } virtual const char *getPassName() const { @@ -97,7 +97,7 @@ bool FPMover::runOnMachineBasicBlock(MachineBasicBlock &MBB) { ++NoopFpDs; continue; } - + unsigned EvenSrcReg = 0, OddSrcReg = 0, EvenDestReg = 0, OddDestReg = 0; getDoubleRegPair(DestDReg, EvenDestReg, OddDestReg); getDoubleRegPair(SrcDReg, EvenSrcReg, OddSrcReg); @@ -111,7 +111,7 @@ bool FPMover::runOnMachineBasicBlock(MachineBasicBlock &MBB) { MI->setDesc(TII->get(SP::FABSS)); else llvm_unreachable("Unknown opcode!"); - + MI->getOperand(0).setReg(EvenDestReg); MI->getOperand(1).setReg(EvenSrcReg); DEBUG(errs() << "FPMover: the modified instr is: " << *MI); @@ -132,7 +132,7 @@ bool FPMover::runOnMachineFunction(MachineFunction &F) { // emitted. Avoid a scan of the instructions to improve compile time. if (TM.getSubtarget().isV9()) return false; - + bool Changed = false; for (MachineFunction::iterator FI = F.begin(), FE = F.end(); FI != FE; ++FI) diff --git a/lib/Target/Sparc/LLVMBuild.txt b/lib/Target/Sparc/LLVMBuild.txt index fe20d2f4bd..7d54d323ac 100644 --- a/lib/Target/Sparc/LLVMBuild.txt +++ b/lib/Target/Sparc/LLVMBuild.txt @@ -28,5 +28,6 @@ has_asmprinter = 1 type = Library name = SparcCodeGen parent = Sparc -required_libraries = AsmPrinter CodeGen Core MC SelectionDAG SparcDesc SparcInfo Support Target +required_libraries = AsmPrinter CodeGen Core MC SelectionDAG SparcDesc + SparcInfo Support Target add_to_library_groups = Sparc diff --git a/lib/Target/Sparc/README.txt b/lib/Target/Sparc/README.txt index c831367e43..34e68cfa78 100644 --- a/lib/Target/Sparc/README.txt +++ b/lib/Target/Sparc/README.txt @@ -38,7 +38,7 @@ t1: 1) should be replaced with a brz in V9 mode. -* Same as above, but emit conditional move on register zero (p192) in V9 +* Same as above, but emit conditional move on register zero (p192) in V9 mode. Testcase: int %t1(int %a, int %b) { @@ -47,12 +47,12 @@ int %t1(int %a, int %b) { ret int %D } -* Emit MULX/[SU]DIVX instructions in V9 mode instead of fiddling +* Emit MULX/[SU]DIVX instructions in V9 mode instead of fiddling with the Y register, if they are faster. * Codegen bswap(load)/store(bswap) -> load/store ASI -* Implement frame pointer elimination, e.g. eliminate save/restore for +* Implement frame pointer elimination, e.g. eliminate save/restore for leaf fns. * Fill delay slots diff --git a/lib/Target/Sparc/Sparc.h b/lib/Target/Sparc/Sparc.h index ce6ae17b6c..90ba27358c 100644 --- a/lib/Target/Sparc/Sparc.h +++ b/lib/Target/Sparc/Sparc.h @@ -51,7 +51,7 @@ namespace llvm { ICC_NEG = 6 , // Negative ICC_VC = 15 , // Overflow Clear ICC_VS = 7 , // Overflow Set - + //FCC_A = 8+16, // Always //FCC_N = 0+16, // Never FCC_U = 7+16, // Unordered @@ -70,7 +70,7 @@ namespace llvm { FCC_O = 15+16 // Ordered }; } - + inline static const char *SPARCCondCodeToString(SPCC::CondCodes CC) { switch (CC) { case SPCC::ICC_NE: return "ne"; diff --git a/lib/Target/Sparc/Sparc.td b/lib/Target/Sparc/Sparc.td index 611f8e8129..d42c40faa1 100644 --- a/lib/Target/Sparc/Sparc.td +++ b/lib/Target/Sparc/Sparc.td @@ -19,7 +19,7 @@ include "llvm/Target/Target.td" //===----------------------------------------------------------------------===// // SPARC Subtarget features. // - + def FeatureV9 : SubtargetFeature<"v9", "IsV9", "true", "Enable SPARC-V9 instructions">; diff --git a/lib/Target/Sparc/SparcAsmPrinter.cpp b/lib/Target/Sparc/SparcAsmPrinter.cpp index 412442974e..b538d5cc0d 100644 --- a/lib/Target/Sparc/SparcAsmPrinter.cpp +++ b/lib/Target/Sparc/SparcAsmPrinter.cpp @@ -60,7 +60,7 @@ namespace { raw_ostream &O); bool printGetPCX(const MachineInstr *MI, unsigned OpNo, raw_ostream &OS); - + virtual bool isBlockOnlyReachableByFallthrough(const MachineBasicBlock *MBB) const; @@ -167,7 +167,7 @@ bool SparcAsmPrinter::printGetPCX(const MachineInstr *MI, unsigned opNum, case MachineOperand::MO_Register: assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) && "Operand is not a physical register "); - assert(MO.getReg() != SP::O7 && + assert(MO.getReg() != SP::O7 && "%o7 is assigned as destination for getpcx!"); operand = "%" + StringRef(getRegisterName(MO.getReg())).lower(); break; @@ -180,15 +180,15 @@ bool SparcAsmPrinter::printGetPCX(const MachineInstr *MI, unsigned opNum, O << "\tcall\t.LLGETPC" << mfNum << '_' << bbNum << '\n' ; O << "\t sethi\t" - << "%hi(_GLOBAL_OFFSET_TABLE_+(.-.LLGETPCH" << mfNum << '_' << bbNum + << "%hi(_GLOBAL_OFFSET_TABLE_+(.-.LLGETPCH" << mfNum << '_' << bbNum << ")), " << operand << '\n' ; O << ".LLGETPC" << mfNum << '_' << bbNum << ":\n" ; - O << "\tor\t" << operand + O << "\tor\t" << operand << ", %lo(_GLOBAL_OFFSET_TABLE_+(.-.LLGETPCH" << mfNum << '_' << bbNum << ")), " << operand << '\n'; - O << "\tadd\t" << operand << ", %o7, " << operand << '\n'; - + O << "\tadd\t" << operand << ", %o7, " << operand << '\n'; + return true; } @@ -246,19 +246,19 @@ isBlockOnlyReachableByFallthrough(const MachineBasicBlock *MBB) const { // then nothing falls through to it. if (MBB->isLandingPad() || MBB->pred_empty()) return false; - + // If there isn't exactly one predecessor, it can't be a fall through. MachineBasicBlock::const_pred_iterator PI = MBB->pred_begin(), PI2 = PI; ++PI2; if (PI2 != MBB->pred_end()) return false; - + // The predecessor has to be immediately before this block. const MachineBasicBlock *Pred = *PI; - + if (!Pred->isLayoutSuccessor(MBB)) return false; - + // Check if the last terminator is an unconditional branch. MachineBasicBlock::const_iterator I = Pred->end(); while (I != Pred->begin() && !(--I)->isTerminator()) @@ -276,7 +276,7 @@ getDebugValueLocation(const MachineInstr *MI) const { } // Force static initialization. -extern "C" void LLVMInitializeSparcAsmPrinter() { +extern "C" void LLVMInitializeSparcAsmPrinter() { RegisterAsmPrinter X(TheSparcTarget); RegisterAsmPrinter Y(TheSparcV9Target); } diff --git a/lib/Target/Sparc/SparcCallingConv.td b/lib/Target/Sparc/SparcCallingConv.td index 54784e0188..a181bcf3d2 100644 --- a/lib/Target/Sparc/SparcCallingConv.td +++ b/lib/Target/Sparc/SparcCallingConv.td @@ -16,7 +16,7 @@ //===----------------------------------------------------------------------===// def CC_Sparc32 : CallingConv<[ - //Custom assign SRet to [sp+64]. + // Custom assign SRet to [sp+64]. CCIfSRet>, // i32 f32 arguments get passed in integer registers if there is space. CCIfType<[i32, f32], CCAssignToReg<[I0, I1, I2, I3, I4, I5]>>, diff --git a/lib/Target/Sparc/SparcFrameLowering.cpp b/lib/Target/Sparc/SparcFrameLowering.cpp index 09e21edcce..7e91bc38d4 100644 --- a/lib/Target/Sparc/SparcFrameLowering.cpp +++ b/lib/Target/Sparc/SparcFrameLowering.cpp @@ -130,7 +130,7 @@ void SparcFrameLowering::emitEpilogue(MachineFunction &MF, } bool SparcFrameLowering::hasReservedCallFrame(const MachineFunction &MF) const { - //Reserve call frame if there are no variable sized objects on the stack + // Reserve call frame if there are no variable sized objects on the stack. return !MF.getFrameInfo()->hasVarSizedObjects(); } @@ -174,17 +174,17 @@ void SparcFrameLowering::remapRegsForLeafProc(MachineFunction &MF) const { MachineRegisterInfo &MRI = MF.getRegInfo(); - //remap %i[0-7] to %o[0-7] + // Remap %i[0-7] to %o[0-7]. for (unsigned reg = SP::I0; reg <= SP::I7; ++reg) { if (!MRI.isPhysRegUsed(reg)) continue; unsigned mapped_reg = (reg - SP::I0 + SP::O0); assert(!MRI.isPhysRegUsed(mapped_reg)); - //Replace I register with O register + // Replace I register with O register. MRI.replaceRegWith(reg, mapped_reg); - //mark the reg unused. + // Mark the reg unused. MRI.setPhysRegUnused(reg); } diff --git a/lib/Target/Sparc/SparcFrameLowering.h b/lib/Target/Sparc/SparcFrameLowering.h index 731b1fb41c..8eaef599ac 100644 --- a/lib/Target/Sparc/SparcFrameLowering.h +++ b/lib/Target/Sparc/SparcFrameLowering.h @@ -44,10 +44,10 @@ public: RegScavenger *RS = NULL) const; private: - //Remap input registers to output registers for leaf procedure. + // Remap input registers to output registers for leaf procedure. void remapRegsForLeafProc(MachineFunction &MF) const; - //Returns true if MF is a leaf procedure. + // Returns true if MF is a leaf procedure. bool isLeafProc(MachineFunction &MF) const; }; diff --git a/lib/Target/Sparc/SparcISelLowering.cpp b/lib/Target/Sparc/SparcISelLowering.cpp index 1aede443ab..8dd29161db 100644 --- a/lib/Target/Sparc/SparcISelLowering.cpp +++ b/lib/Target/Sparc/SparcISelLowering.cpp @@ -40,7 +40,7 @@ static bool CC_Sparc_Assign_SRet(unsigned &ValNo, MVT &ValVT, { assert (ArgFlags.isSRet()); - //Assign SRet argument + // Assign SRet argument. State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT, 0, LocVT, LocInfo)); @@ -54,18 +54,18 @@ static bool CC_Sparc_Assign_f64(unsigned &ValNo, MVT &ValVT, static const uint16_t RegList[] = { SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5 }; - //Try to get first reg + // Try to get first reg. if (unsigned Reg = State.AllocateReg(RegList, 6)) { State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo)); } else { - //Assign whole thing in stack + // Assign whole thing in stack. State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT, State.AllocateStack(8,4), LocVT, LocInfo)); return true; } - //Try to get second reg + // Try to get second reg. if (unsigned Reg = State.AllocateReg(RegList, 6)) State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo)); else @@ -206,7 +206,7 @@ SparcTargetLowering::LowerReturn_32(SDValue Chain, RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); } - unsigned RetAddrOffset = 8; //Call Inst + Delay Slot + unsigned RetAddrOffset = 8; // Call Inst + Delay Slot // If the function returns a struct, copy the SRetReturnReg to I0 if (MF.getFunction()->hasStructRetAttr()) { SparcMachineFunctionInfo *SFI = MF.getInfo(); @@ -351,7 +351,7 @@ LowerFormalArguments_32(SDValue Chain, CCValAssign &VA = ArgLocs[i]; if (i == 0 && Ins[i].Flags.isSRet()) { - //Get SRet from [%fp+64] + // Get SRet from [%fp+64]. int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, 64, true); SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); SDValue Arg = DAG.getLoad(MVT::i32, dl, Chain, FIPtr, @@ -410,7 +410,7 @@ LowerFormalArguments_32(SDValue Chain, if (VA.needsCustom()) { assert(VA.getValVT() == MVT::f64); - //If it is double-word aligned, just load. + // If it is double-word aligned, just load. if (Offset % 8 == 0) { int FI = MF.getFrameInfo()->CreateFixedObject(8, Offset, @@ -470,7 +470,7 @@ LowerFormalArguments_32(SDValue Chain, } if (MF.getFunction()->hasStructRetAttr()) { - //Copy the SRet Argument to SRetReturnReg + // Copy the SRet Argument to SRetReturnReg. SparcMachineFunctionInfo *SFI = MF.getInfo(); unsigned Reg = SFI->getSRetReturnReg(); if (!Reg) { @@ -680,7 +680,7 @@ SparcTargetLowering::LowerCall_32(TargetLowering::CallLoweringInfo &CLI, MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); - //Create local copies for byval args. + // Create local copies for byval args. SmallVector ByValArgs; for (unsigned i = 0, e = Outs.size(); i != e; ++i) { ISD::ArgFlagsTy Flags = Outs[i].Flags; @@ -696,8 +696,8 @@ SparcTargetLowering::LowerCall_32(TargetLowering::CallLoweringInfo &CLI, SDValue SizeNode = DAG.getConstant(Size, MVT::i32); Chain = DAG.getMemcpy(Chain, dl, FIPtr, Arg, SizeNode, Align, - false, //isVolatile, - (Size <= 32), //AlwaysInline if size <= 32 + false, // isVolatile, + (Size <= 32), // AlwaysInline if size <= 32 MachinePointerInfo(), MachinePointerInfo()); ByValArgs.push_back(FIPtr); } @@ -719,7 +719,7 @@ SparcTargetLowering::LowerCall_32(TargetLowering::CallLoweringInfo &CLI, ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags; - //Use local copy if it is a byval arg. + // Use local copy if it is a byval arg. if (Flags.isByVal()) Arg = ByValArgs[byvalArgIdx++]; @@ -759,7 +759,7 @@ SparcTargetLowering::LowerCall_32(TargetLowering::CallLoweringInfo &CLI, if (VA.isMemLoc()) { unsigned Offset = VA.getLocMemOffset() + StackOffset; - //if it is double-word aligned, just store. + // if it is double-word aligned, just store. if (Offset % 8 == 0) { SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32); SDValue PtrOff = DAG.getIntPtrConstant(Offset); @@ -792,7 +792,7 @@ SparcTargetLowering::LowerCall_32(TargetLowering::CallLoweringInfo &CLI, if (NextVA.isRegLoc()) { RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), Lo)); } else { - //Store the low part in stack. + // Store the low part in stack. unsigned Offset = NextVA.getLocMemOffset() + StackOffset; SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32); SDValue PtrOff = DAG.getIntPtrConstant(Offset); @@ -1398,11 +1398,12 @@ const char *SparcTargetLowering::getTargetNodeName(unsigned Opcode) const { /// isMaskedValueZeroForTargetNode - Return true if 'Op & Mask' is known to /// be zero. Op is expected to be a target specific node. Used by DAG /// combiner. -void SparcTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op, - APInt &KnownZero, - APInt &KnownOne, - const SelectionDAG &DAG, - unsigned Depth) const { +void SparcTargetLowering::computeMaskedBitsForTargetNode + (const SDValue Op, + APInt &KnownZero, + APInt &KnownOne, + const SelectionDAG &DAG, + unsigned Depth) const { APInt KnownZero2, KnownOne2; KnownZero = KnownOne = APInt(KnownZero.getBitWidth(), 0); @@ -1625,7 +1626,7 @@ static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG, MachineFunction &MF = DAG.getMachineFunction(); SparcMachineFunctionInfo *FuncInfo = MF.getInfo(); - //Need frame address to find the address of VarArgsFrameIndex + // Need frame address to find the address of VarArgsFrameIndex. MF.getFrameInfo()->setFrameAddressIsTaken(true); // vastart just stores the address of the VarArgsFrameIndex slot into the @@ -1734,7 +1735,7 @@ static SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) { if (depth == 0) RetAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, RetReg, VT); else { - //Need frame address to find return address of the caller + // Need frame address to find return address of the caller. MFI->setFrameAddressIsTaken(true); // flush first to make sure the windowed registers' values are in stack diff --git a/lib/Target/Sparc/SparcInstrFormats.td b/lib/Target/Sparc/SparcInstrFormats.td index e7fde085be..6cdf6bc25b 100644 --- a/lib/Target/Sparc/SparcInstrFormats.td +++ b/lib/Target/Sparc/SparcInstrFormats.td @@ -7,14 +7,15 @@ // //===----------------------------------------------------------------------===// -class InstSP pattern> : Instruction { +class InstSP pattern> + : Instruction { field bits<32> Inst; let Namespace = "SP"; bits<2> op; let Inst{31-30} = op; // Top two bits are the 'op' field - + dag OutOperandList = outs; dag InOperandList = ins; let AsmString = asmstr; @@ -46,7 +47,7 @@ class F2_1 op2Val, dag outs, dag ins, string asmstr, list pattern> let Inst{29-25} = rd; } -class F2_2 condVal, bits<3> op2Val, dag outs, dag ins, string asmstr, +class F2_2 condVal, bits<3> op2Val, dag outs, dag ins, string asmstr, list pattern> : F2 { bits<4> cond; bit annul = 0; // currently unused @@ -88,7 +89,7 @@ class F3_1 opVal, bits<6> op3val, dag outs, dag ins, let Inst{4-0} = rs2; } -class F3_2 opVal, bits<6> op3val, dag outs, dag ins, +class F3_2 opVal, bits<6> op3val, dag outs, dag ins, string asmstr, list pattern> : F3 { bits<13> simm13; diff --git a/lib/Target/Sparc/SparcInstrInfo.cpp b/lib/Target/Sparc/SparcInstrInfo.cpp index 546292ce64..46033b6653 100644 --- a/lib/Target/Sparc/SparcInstrInfo.cpp +++ b/lib/Target/Sparc/SparcInstrInfo.cpp @@ -141,15 +141,15 @@ bool SparcInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, if (I->isDebugValue()) continue; - //When we see a non-terminator, we are done + // When we see a non-terminator, we are done. if (!isUnpredicatedTerminator(I)) break; - //Terminator is not a branch + // Terminator is not a branch. if (!I->isBranch()) return true; - //Handle Unconditional branches + // Handle Unconditional branches. if (I->getOpcode() == SP::BA) { UnCondBrIter = I; @@ -178,7 +178,7 @@ bool SparcInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, unsigned Opcode = I->getOpcode(); if (Opcode != SP::BCOND && Opcode != SP::FBCOND) - return true; //Unknown Opcode + return true; // Unknown Opcode. SPCC::CondCodes BranchCode = (SPCC::CondCodes)I->getOperand(1).getImm(); @@ -187,7 +187,7 @@ bool SparcInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, if (AllowModify && UnCondBrIter != MBB.end() && MBB.isLayoutSuccessor(TargetBB)) { - //Transform the code + // Transform the code // // brCC L1 // ba L2 @@ -221,8 +221,8 @@ bool SparcInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, Cond.push_back(MachineOperand::CreateImm(BranchCode)); continue; } - //FIXME: Handle subsequent conditional branches - //For now, we can't handle multiple conditional branches + // FIXME: Handle subsequent conditional branches. + // For now, we can't handle multiple conditional branches. return true; } return false; @@ -243,7 +243,7 @@ SparcInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB, return 1; } - //Conditional branch + // Conditional branch unsigned CC = Cond[0].getImm(); if (IsIntegerCC(CC)) diff --git a/lib/Target/Sparc/SparcInstrInfo.h b/lib/Target/Sparc/SparcInstrInfo.h index 204f69855c..a0a0ffd816 100644 --- a/lib/Target/Sparc/SparcInstrInfo.h +++ b/lib/Target/Sparc/SparcInstrInfo.h @@ -53,7 +53,7 @@ public: /// any side effects other than loading from the stack slot. virtual unsigned isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const; - + /// isStoreToStackSlot - If the specified machine instruction is a direct /// store to a stack slot, return the virtual or physical register number of /// the source reg along with the FrameIndex of the loaded stack slot. If @@ -86,7 +86,7 @@ public: MachineBasicBlock::iterator I, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const; - + virtual void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, @@ -98,7 +98,7 @@ public: unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const; - + unsigned getGlobalBaseReg(MachineFunction *MF) const; }; diff --git a/lib/Target/Sparc/SparcInstrInfo.td b/lib/Target/Sparc/SparcInstrInfo.td index 8f01d83f23..b2f98548c5 100644 --- a/lib/Target/Sparc/SparcInstrInfo.td +++ b/lib/Target/Sparc/SparcInstrInfo.td @@ -89,9 +89,9 @@ def calltarget : Operand; let PrintMethod = "printCCOperand" in def CCOp : Operand; -def SDTSPcmpfcc : +def SDTSPcmpfcc : SDTypeProfile<0, 2, [SDTCisFP<0>, SDTCisSameAs<0, 1>]>; -def SDTSPbrcc : +def SDTSPbrcc : SDTypeProfile<0, 2, [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>; def SDTSPselectcc : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32>]>; @@ -186,7 +186,7 @@ def FCC_O : FCC_VAL<29>; // Ordered /// F3_12 multiclass - Define a normal F3_1/F3_2 pattern in one shot. multiclass F3_12 Op3Val, SDNode OpNode> { - def rr : F3_1<2, Op3Val, + def rr : F3_1<2, Op3Val, (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c), !strconcat(OpcStr, " $b, $c, $dst"), [(set i32:$dst, (OpNode i32:$b, i32:$c))]>; @@ -199,7 +199,7 @@ multiclass F3_12 Op3Val, SDNode OpNode> { /// F3_12np multiclass - Define a normal F3_1/F3_2 pattern in one shot, with no /// pattern. multiclass F3_12np Op3Val> { - def rr : F3_1<2, Op3Val, + def rr : F3_1<2, Op3Val, (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c), !strconcat(OpcStr, " $b, $c, $dst"), []>; def ri : F3_2<2, Op3Val, @@ -243,7 +243,7 @@ let hasSideEffects = 1, mayStore = 1 in { def UNIMP : F2_1<0b000, (outs), (ins i32imm:$val), "unimp $val", []>; -// FpMOVD/FpNEGD/FpABSD - These are lowered to single-precision ops by the +// FpMOVD/FpNEGD/FpABSD - These are lowered to single-precision ops by the // fpmover pass. let Predicates = [HasNoV9] in { // Only emit these in V8 mode. def FpMOVD : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$src), @@ -259,8 +259,8 @@ let Predicates = [HasNoV9] in { // Only emit these in V8 mode. // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after // instruction selection into a branch sequence. This has to handle all // permutations of selection between i32/f32/f64 on ICC and FCC. - // Expanded after instruction selection. -let Uses = [ICC], usesCustomInserter = 1 in { +// Expanded after instruction selection. +let Uses = [ICC], usesCustomInserter = 1 in { def SELECT_CC_Int_ICC : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, i32imm:$Cond), "; SELECT_CC_Int_ICC PSEUDO!", @@ -465,7 +465,7 @@ def LEA_ADDri : F3_2<2, 0b000000, "add ${addr:arith}, $dst", [(set iPTR:$dst, ADDRri:$addr)]>; -let Defs = [ICC] in +let Defs = [ICC] in defm ADDCC : F3_12<"addcc", 0b010000, addc>; let Uses = [ICC] in @@ -473,14 +473,14 @@ let Uses = [ICC] in // Section B.15 - Subtract Instructions, p. 110 defm SUB : F3_12 <"sub" , 0b000100, sub>; -let Uses = [ICC] in +let Uses = [ICC] in defm SUBX : F3_12 <"subx" , 0b001100, sube>; -let Defs = [ICC] in +let Defs = [ICC] in defm SUBCC : F3_12 <"subcc", 0b010100, SPcmpicc>; let Uses = [ICC], Defs = [ICC] in - def SUBXCCrr: F3_1<2, 0b011100, + def SUBXCCrr: F3_1<2, 0b011100, (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c), "subxcc $b, $c, $dst", []>; @@ -516,7 +516,7 @@ let isBarrier = 1 in "ba $dst", [(br bb:$dst)]>; -//Indirect Branch +// Indirect branch instructions. let isTerminator = 1, isBarrier = 1, hasDelaySlot = 1, isBranch =1, isIndirectBranch = 1 in { @@ -567,7 +567,7 @@ let Uses = [O6], let op = 1; let Inst{29-0} = disp; } - + // indirect calls def JMPLrr : F3_1<2, 0b111000, (outs), (ins MEMrr:$ptr, variable_ops), @@ -580,7 +580,7 @@ let Uses = [O6], } // Section B.28 - Read State Register Instructions -let Uses = [Y] in +let Uses = [Y] in def RDY : F3_1<2, 0b101000, (outs IntRegs:$dst), (ins), "rd %y, $dst", []>; @@ -599,7 +599,7 @@ def FITOS : F3_3<2, 0b110100, 0b011000100, (outs FPRegs:$dst), (ins FPRegs:$src), "fitos $src, $dst", [(set FPRegs:$dst, (SPitof FPRegs:$src))]>; -def FITOD : F3_3<2, 0b110100, 0b011001000, +def FITOD : F3_3<2, 0b110100, 0b011001000, (outs DFPRegs:$dst), (ins FPRegs:$src), "fitod $src, $dst", [(set DFPRegs:$dst, (SPitof FPRegs:$src))]>; @@ -615,7 +615,7 @@ def FDTOI : F3_3<2, 0b110100, 0b011010010, [(set FPRegs:$dst, (SPftoi DFPRegs:$src))]>; // Convert between Floating-point Formats Instructions, p. 143 -def FSTOD : F3_3<2, 0b110100, 0b011001001, +def FSTOD : F3_3<2, 0b110100, 0b011001001, (outs DFPRegs:$dst), (ins FPRegs:$src), "fstod $src, $dst", [(set f64:$dst, (fextend f32:$src))]>; @@ -628,22 +628,22 @@ def FDTOS : F3_3<2, 0b110100, 0b011000110, def FMOVS : F3_3<2, 0b110100, 0b000000001, (outs FPRegs:$dst), (ins FPRegs:$src), "fmovs $src, $dst", []>; -def FNEGS : F3_3<2, 0b110100, 0b000000101, +def FNEGS : F3_3<2, 0b110100, 0b000000101, (outs FPRegs:$dst), (ins FPRegs:$src), "fnegs $src, $dst", [(set f32:$dst, (fneg f32:$src))]>; -def FABSS : F3_3<2, 0b110100, 0b000001001, +def FABSS : F3_3<2, 0b110100, 0b000001001, (outs FPRegs:$dst), (ins FPRegs:$src), "fabss $src, $dst", [(set f32:$dst, (fabs f32:$src))]>; // Floating-point Square Root Instructions, p.145 -def FSQRTS : F3_3<2, 0b110100, 0b000101001, +def FSQRTS : F3_3<2, 0b110100, 0b000101001, (outs FPRegs:$dst), (ins FPRegs:$src), "fsqrts $src, $dst", [(set f32:$dst, (fsqrt f32:$src))]>; -def FSQRTD : F3_3<2, 0b110100, 0b000101010, +def FSQRTD : F3_3<2, 0b110100, 0b000101010, (outs DFPRegs:$dst), (ins DFPRegs:$src), "fsqrtd $src, $dst", [(set f64:$dst, (fsqrt f64:$src))]>; @@ -766,11 +766,11 @@ let Predicates = [HasV9] in { def FMOVD : F3_3<2, 0b110100, 0b000000010, (outs DFPRegs:$dst), (ins DFPRegs:$src), "fmovd $src, $dst", []>; - def FNEGD : F3_3<2, 0b110100, 0b000000110, + def FNEGD : F3_3<2, 0b110100, 0b000000110, (outs DFPRegs:$dst), (ins DFPRegs:$src), "fnegd $src, $dst", [(set f64:$dst, (fneg f64:$src))]>; - def FABSD : F3_3<2, 0b110100, 0b000001010, + def FABSD : F3_3<2, 0b110100, 0b000001010, (outs DFPRegs:$dst), (ins DFPRegs:$src), "fabsd $src, $dst", [(set f64:$dst, (fabs f64:$src))]>; @@ -778,7 +778,7 @@ let Predicates = [HasV9] in { // POPCrr - This does a ctpop of a 64-bit register. As such, we have to clear // the top 32-bits before using it. To do this clearing, we use a SLLri X,0. -def POPCrr : F3_1<2, 0b101110, +def POPCrr : F3_1<2, 0b101110, (outs IntRegs:$dst), (ins IntRegs:$src), "popc $src, $dst", []>, Requires<[HasV9]>; def : Pat<(ctpop i32:$src), @@ -817,7 +817,7 @@ def : Pat<(add iPTR:$r, (SPlo tconstpool:$in)), (ADDri $r, tconstpool:$in)>; def : Pat<(add iPTR:$r, (SPlo tblockaddress:$in)), (ADDri $r, tblockaddress:$in)>; -// Calls: +// Calls: def : Pat<(call tglobaladdr:$dst), (CALL tglobaladdr:$dst)>; def : Pat<(call texternalsym:$dst), diff --git a/lib/Target/Sparc/SparcRegisterInfo.cpp b/lib/Target/Sparc/SparcRegisterInfo.cpp index 6d7c9f5609..fe91a3d070 100644 --- a/lib/Target/Sparc/SparcRegisterInfo.cpp +++ b/lib/Target/Sparc/SparcRegisterInfo.cpp @@ -50,13 +50,13 @@ BitVector SparcRegisterInfo::getReservedRegs(const MachineFunction &MF) const { // FIXME: G1 reserved for now for large imm generation by frame code. Reserved.set(SP::G1); - //G1-G4 can be used in applications. + // G1-G4 can be used in applications. if (ReserveAppRegisters) { Reserved.set(SP::G2); Reserved.set(SP::G3); Reserved.set(SP::G4); } - //G5 is not reserved in 64 bit mode. + // G5 is not reserved in 64 bit mode. if (!Subtarget.is64Bit()) Reserved.set(SP::G5); @@ -93,7 +93,7 @@ SparcRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, SparcMachineFunctionInfo *FuncInfo = MF.getInfo(); unsigned FramePtr = SP::I6; if (FuncInfo->isLeafProc()) { - //Use %sp and adjust offset if needed. + // Use %sp and adjust offset if needed. FramePtr = SP::O6; int stackSize = MF.getFrameInfo()->getStackSize(); Offset += (stackSize) ? Subtarget.getAdjustedFrameSize(stackSize) : 0 ; @@ -106,7 +106,7 @@ SparcRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, MI.getOperand(FIOperandNum).ChangeToRegister(FramePtr, false); MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset); } else { - // Otherwise, emit a G1 = SETHI %hi(offset). FIXME: it would be better to + // Otherwise, emit a G1 = SETHI %hi(offset). FIXME: it would be better to // scavenge a register here instead of reserving G1 all of the time. unsigned OffHi = (unsigned)Offset >> 10U; BuildMI(*MI.getParent(), II, dl, TII.get(SP::SETHIi), SP::G1).addImm(OffHi); diff --git a/lib/Target/Sparc/SparcRegisterInfo.td b/lib/Target/Sparc/SparcRegisterInfo.td index b57fd3ddaf..a59c4426f0 100644 --- a/lib/Target/Sparc/SparcRegisterInfo.td +++ b/lib/Target/Sparc/SparcRegisterInfo.td @@ -8,7 +8,7 @@ //===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===// -// Declarations that describe the Sparc register file +// Declarations that describe the Sparc register file //===----------------------------------------------------------------------===// class SparcReg : Register { @@ -52,68 +52,68 @@ def Y : SparcCtrlReg<"Y">; // Integer registers def G0 : Ri< 0, "G0">, DwarfRegNum<[0]>; def G1 : Ri< 1, "G1">, DwarfRegNum<[1]>; -def G2 : Ri< 2, "G2">, DwarfRegNum<[2]>; +def G2 : Ri< 2, "G2">, DwarfRegNum<[2]>; def G3 : Ri< 3, "G3">, DwarfRegNum<[3]>; def G4 : Ri< 4, "G4">, DwarfRegNum<[4]>; -def G5 : Ri< 5, "G5">, DwarfRegNum<[5]>; +def G5 : Ri< 5, "G5">, DwarfRegNum<[5]>; def G6 : Ri< 6, "G6">, DwarfRegNum<[6]>; def G7 : Ri< 7, "G7">, DwarfRegNum<[7]>; def O0 : Ri< 8, "O0">, DwarfRegNum<[8]>; def O1 : Ri< 9, "O1">, DwarfRegNum<[9]>; -def O2 : Ri<10, "O2">, DwarfRegNum<[10]>; +def O2 : Ri<10, "O2">, DwarfRegNum<[10]>; def O3 : Ri<11, "O3">, DwarfRegNum<[11]>; def O4 : Ri<12, "O4">, DwarfRegNum<[12]>; -def O5 : Ri<13, "O5">, DwarfRegNum<[13]>; +def O5 : Ri<13, "O5">, DwarfRegNum<[13]>; def O6 : Ri<14, "SP">, DwarfRegNum<[14]>; def O7 : Ri<15, "O7">, DwarfRegNum<[15]>; def L0 : Ri<16, "L0">, DwarfRegNum<[16]>; def L1 : Ri<17, "L1">, DwarfRegNum<[17]>; -def L2 : Ri<18, "L2">, DwarfRegNum<[18]>; +def L2 : Ri<18, "L2">, DwarfRegNum<[18]>; def L3 : Ri<19, "L3">, DwarfRegNum<[19]>; def L4 : Ri<20, "L4">, DwarfRegNum<[20]>; -def L5 : Ri<21, "L5">, DwarfRegNum<[21]>; +def L5 : Ri<21, "L5">, DwarfRegNum<[21]>; def L6 : Ri<22, "L6">, DwarfRegNum<[22]>; def L7 : Ri<23, "L7">, DwarfRegNum<[23]>; def I0 : Ri<24, "I0">, DwarfRegNum<[24]>; def I1 : Ri<25, "I1">, DwarfRegNum<[25]>; -def I2 : Ri<26, "I2">, DwarfRegNum<[26]>; +def I2 : Ri<26, "I2">, DwarfRegNum<[26]>; def I3 : Ri<27, "I3">, DwarfRegNum<[27]>; def I4 : Ri<28, "I4">, DwarfRegNum<[28]>; -def I5 : Ri<29, "I5">, DwarfRegNum<[29]>; +def I5 : Ri<29, "I5">, DwarfRegNum<[29]>; def I6 : Ri<30, "FP">, DwarfRegNum<[30]>; def I7 : Ri<31, "I7">, DwarfRegNum<[31]>; // Floating-point registers def F0 : Rf< 0, "F0">, DwarfRegNum<[32]>; def F1 : Rf< 1, "F1">, DwarfRegNum<[33]>; -def F2 : Rf< 2, "F2">, DwarfRegNum<[34]>; +def F2 : Rf< 2, "F2">, DwarfRegNum<[34]>; def F3 : Rf< 3, "F3">, DwarfRegNum<[35]>; def F4 : Rf< 4, "F4">, DwarfRegNum<[36]>; -def F5 : Rf< 5, "F5">, DwarfRegNum<[37]>; +def F5 : Rf< 5, "F5">, DwarfRegNum<[37]>; def F6 : Rf< 6, "F6">, DwarfRegNum<[38]>; def F7 : Rf< 7, "F7">, DwarfRegNum<[39]>; -def F8 : Rf< 8, "F8">, DwarfRegNum<[40]>; +def F8 : Rf< 8, "F8">, DwarfRegNum<[40]>; def F9 : Rf< 9, "F9">, DwarfRegNum<[41]>; def F10 : Rf<10, "F10">, DwarfRegNum<[42]>; -def F11 : Rf<11, "F11">, DwarfRegNum<[43]>; +def F11 : Rf<11, "F11">, DwarfRegNum<[43]>; def F12 : Rf<12, "F12">, DwarfRegNum<[44]>; def F13 : Rf<13, "F13">, DwarfRegNum<[45]>; -def F14 : Rf<14, "F14">, DwarfRegNum<[46]>; +def F14 : Rf<14, "F14">, DwarfRegNum<[46]>; def F15 : Rf<15, "F15">, DwarfRegNum<[47]>; def F16 : Rf<16, "F16">, DwarfRegNum<[48]>; -def F17 : Rf<17, "F17">, DwarfRegNum<[49]>; +def F17 : Rf<17, "F17">, DwarfRegNum<[49]>; def F18 : Rf<18, "F18">, DwarfRegNum<[50]>; def F19 : Rf<19, "F19">, DwarfRegNum<[51]>; -def F20 : Rf<20, "F20">, DwarfRegNum<[52]>; +def F20 : Rf<20, "F20">, DwarfRegNum<[52]>; def F21 : Rf<21, "F21">, DwarfRegNum<[53]>; def F22 : Rf<22, "F22">, DwarfRegNum<[54]>; def F23 : Rf<23, "F23">, DwarfRegNum<[55]>; def F24 : Rf<24, "F24">, DwarfRegNum<[56]>; def F25 : Rf<25, "F25">, DwarfRegNum<[57]>; -def F26 : Rf<26, "F26">, DwarfRegNum<[58]>; +def F26 : Rf<26, "F26">, DwarfRegNum<[58]>; def F27 : Rf<27, "F27">, DwarfRegNum<[59]>; def F28 : Rf<28, "F28">, DwarfRegNum<[60]>; -def F29 : Rf<29, "F29">, DwarfRegNum<[61]>; +def F29 : Rf<29, "F29">, DwarfRegNum<[61]>; def F30 : Rf<30, "F30">, DwarfRegNum<[62]>; def F31 : Rf<31, "F31">, DwarfRegNum<[63]>; diff --git a/lib/Target/Sparc/SparcSubtarget.cpp b/lib/Target/Sparc/SparcSubtarget.cpp index ba129ec926..f9ce0984f4 100644 --- a/lib/Target/Sparc/SparcSubtarget.cpp +++ b/lib/Target/Sparc/SparcSubtarget.cpp @@ -31,7 +31,7 @@ SparcSubtarget::SparcSubtarget(const std::string &TT, const std::string &CPU, V8DeprecatedInsts(false), IsVIS(false), Is64Bit(is64Bit) { - + // Determine default and user specified characteristics std::string CPUName = CPU; if (CPUName.empty()) { diff --git a/lib/Target/Sparc/SparcSubtarget.h b/lib/Target/Sparc/SparcSubtarget.h index 30014aec27..2bf599d912 100644 --- a/lib/Target/Sparc/SparcSubtarget.h +++ b/lib/Target/Sparc/SparcSubtarget.h @@ -29,7 +29,7 @@ class SparcSubtarget : public SparcGenSubtargetInfo { bool V8DeprecatedInsts; bool IsVIS; bool Is64Bit; - + public: SparcSubtarget(const std::string &TT, const std::string &CPU, const std::string &FS, bool is64bit); @@ -37,11 +37,11 @@ public: bool isV9() const { return IsV9; } bool isVIS() const { return IsVIS; } bool useDeprecatedV8Instructions() const { return V8DeprecatedInsts; } - - /// ParseSubtargetFeatures - Parses features string setting specified + + /// ParseSubtargetFeatures - Parses features string setting specified /// subtarget options. Definition of function is auto generated by tblgen. void ParseSubtargetFeatures(StringRef CPU, StringRef FS); - + bool is64Bit() const { return Is64Bit; } std::string getDataLayout() const { const char *p; -- cgit v1.2.3