From 30ec8a3658b1f06bb94d392c55feb7f107517bf8 Mon Sep 17 00:00:00 2001 From: Venkatraman Govindaraju Date: Thu, 26 Sep 2013 15:11:00 +0000 Subject: [Sparc] Implements exception handling in SPARC with DwarfCFI. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191432 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/CodeGen/AsmPrinter/AsmPrinterDwarf.cpp | 3 + lib/Target/Sparc/MCTargetDesc/SparcMCAsmInfo.cpp | 2 + lib/Target/Sparc/SparcFrameLowering.cpp | 19 ++++ lib/Target/Sparc/SparcISelLowering.cpp | 6 +- test/CodeGen/SPARC/exception.ll | 112 +++++++++++++++++++++++ 5 files changed, 138 insertions(+), 4 deletions(-) create mode 100644 test/CodeGen/SPARC/exception.ll diff --git a/lib/CodeGen/AsmPrinter/AsmPrinterDwarf.cpp b/lib/CodeGen/AsmPrinter/AsmPrinterDwarf.cpp index c48445f4d4..b92f49cfae 100644 --- a/lib/CodeGen/AsmPrinter/AsmPrinterDwarf.cpp +++ b/lib/CodeGen/AsmPrinter/AsmPrinterDwarf.cpp @@ -185,6 +185,9 @@ void AsmPrinter::emitCFIInstruction(const MCCFIInstruction &Inst) const { case MCCFIInstruction::OpOffset: OutStreamer.EmitCFIOffset(Inst.getRegister(), Inst.getOffset()); break; + case MCCFIInstruction::OpRegister: + OutStreamer.EmitCFIRegister(Inst.getRegister(), Inst.getRegister2()); + break; case MCCFIInstruction::OpWindowSave: OutStreamer.EmitCFIWindowSave(); break; diff --git a/lib/Target/Sparc/MCTargetDesc/SparcMCAsmInfo.cpp b/lib/Target/Sparc/MCTargetDesc/SparcMCAsmInfo.cpp index 45cfe033bb..06b1df6dbf 100644 --- a/lib/Target/Sparc/MCTargetDesc/SparcMCAsmInfo.cpp +++ b/lib/Target/Sparc/MCTargetDesc/SparcMCAsmInfo.cpp @@ -36,6 +36,8 @@ SparcELFMCAsmInfo::SparcELFMCAsmInfo(StringRef TT) { HasLEB128 = true; SupportsDebugInformation = true; + ExceptionsType = ExceptionHandling::DwarfCFI; + SunStyleELFSectionSwitchSyntax = true; UsesELFSectionDirectiveForBSS = true; diff --git a/lib/Target/Sparc/SparcFrameLowering.cpp b/lib/Target/Sparc/SparcFrameLowering.cpp index 536e466ca3..1f9cac54b8 100644 --- a/lib/Target/Sparc/SparcFrameLowering.cpp +++ b/lib/Target/Sparc/SparcFrameLowering.cpp @@ -70,6 +70,25 @@ void SparcFrameLowering::emitPrologue(MachineFunction &MF) const { BuildMI(MBB, MBBI, dl, TII.get(SAVErr), SP::O6) .addReg(SP::O6).addReg(SP::G1); } + MachineModuleInfo &MMI = MF.getMMI(); + const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo(); + MCSymbol *FrameLabel = MMI.getContext().CreateTempSymbol(); + BuildMI(MBB, MBBI, dl, TII.get(SP::PROLOG_LABEL)).addSym(FrameLabel); + + unsigned regFP = MRI->getDwarfRegNum(SP::I6, true); + + // Emit ".cfi_def_cfa_register 30". + MMI.addFrameInst(MCCFIInstruction::createDefCfaRegister(FrameLabel, + regFP)); + // Emit ".cfi_window_save". + MMI.addFrameInst(MCCFIInstruction::createWindowSave(FrameLabel)); + + unsigned regInRA = MRI->getDwarfRegNum(SP::I7, true); + unsigned regOutRA = MRI->getDwarfRegNum(SP::O7, true); + // Emit ".cfi_register 15, 31". + MMI.addFrameInst(MCCFIInstruction::createRegister(FrameLabel, + regOutRA, + regInRA)); } void SparcFrameLowering:: diff --git a/lib/Target/Sparc/SparcISelLowering.cpp b/lib/Target/Sparc/SparcISelLowering.cpp index 86bac7e3d8..cdba998244 100644 --- a/lib/Target/Sparc/SparcISelLowering.cpp +++ b/lib/Target/Sparc/SparcISelLowering.cpp @@ -1432,8 +1432,6 @@ SparcTargetLowering::SparcTargetLowering(TargetMachine &TM) setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand); setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand); - setOperationAction(ISD::EH_LABEL, MVT::Other, Expand); - // VASTART needs to be custom lowered to use the VarArgsFrameIndex. setOperationAction(ISD::VASTART , MVT::Other, Custom); // VAARG needs to be lowered to not do unaligned accesses for doubles. @@ -1446,8 +1444,8 @@ SparcTargetLowering::SparcTargetLowering(TargetMachine &TM) setOperationAction(ISD::STACKRESTORE , MVT::Other, Expand); setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom); - // No debug info support yet. - setOperationAction(ISD::EH_LABEL, MVT::Other, Expand); + setExceptionPointerRegister(SP::I0); + setExceptionSelectorRegister(SP::I1); setStackPointerRegisterToSaveRestore(SP::O6); diff --git a/test/CodeGen/SPARC/exception.ll b/test/CodeGen/SPARC/exception.ll new file mode 100644 index 0000000000..cb5b6e5c11 --- /dev/null +++ b/test/CodeGen/SPARC/exception.ll @@ -0,0 +1,112 @@ +; RUN: llc < %s -march=sparc | FileCheck %s + + +%struct.__fundamental_type_info_pseudo = type { %struct.__type_info_pseudo } +%struct.__type_info_pseudo = type { i8*, i8* } + +@_ZTIi = external constant %struct.__fundamental_type_info_pseudo +@_ZTIf = external constant %struct.__fundamental_type_info_pseudo +@.cst = linker_private unnamed_addr constant [12 x i8] c"catched int\00", align 64 +@.cst1 = linker_private unnamed_addr constant [14 x i8] c"catched float\00", align 64 + +; CHECK-LABEL: main: +; CHECK: .cfi_startproc +; CHECK: .cfi_def_cfa_register 30 +; CHECK: .cfi_window_save +; CHECK: .cfi_register 15, 31 + +; CHECK: call __cxa_throw +; CHECK: call __cxa_throw + +; CHECK: call __cxa_begin_catch +; CHECK: call __cxa_end_catch + +; CHECK: call __cxa_begin_catch +; CHECK: call __cxa_end_catch + +; CHECK: .cfi_endproc + +define i32 @main(i32 %argc, i8** nocapture readnone %argv) unnamed_addr #0 { +entry: + %0 = icmp eq i32 %argc, 2 + %1 = tail call i8* @__cxa_allocate_exception(i32 4) #1 + br i1 %0, label %"3", label %"4" + +"3": ; preds = %entry + %2 = bitcast i8* %1 to i32* + store i32 0, i32* %2, align 4 + invoke void @__cxa_throw(i8* %1, i8* bitcast (%struct.__fundamental_type_info_pseudo* @_ZTIi to i8*), void (i8*)* null) #2 + to label %3 unwind label %"8" + +;