From c567b1cd0d6bf973a21df4b5c8cae37e5e7518f8 Mon Sep 17 00:00:00 2001 From: Akira Hatanaka Date: Thu, 13 Dec 2012 02:05:02 +0000 Subject: [mips] Delete all floating point instruction classes that are no longer used. No functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170084 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Mips/MipsCondMov.td | 33 +-------- lib/Target/Mips/MipsInstrFPU.td | 118 -------------------------------- lib/Target/Mips/MipsInstrFormats.td | 130 ------------------------------------ 3 files changed, 2 insertions(+), 279 deletions(-) diff --git a/lib/Target/Mips/MipsCondMov.td b/lib/Target/Mips/MipsCondMov.td index b78c2bbf66..5e21d4dc2b 100644 --- a/lib/Target/Mips/MipsCondMov.td +++ b/lib/Target/Mips/MipsCondMov.td @@ -25,37 +25,6 @@ class CondMovIntInt funct, } // cond:int, data:float -class CondMovIntFP fmt, - bits<6> func, string instr_asm> : - FFR<0x11, func, fmt, (outs DRC:$fd), (ins DRC:$fs, CRC:$rt, DRC:$F), - !strconcat(instr_asm, "\t$fd, $fs, $rt"), []> { - bits<5> rt; - let ft = rt; - let Constraints = "$F = $fd"; -} - -// cond:float, data:int -class CondMovFPInt tf, - string instr_asm> : - FCMOV { - let cc = 0; - let Uses = [FCR31]; - let Constraints = "$F = $rd"; -} - -// cond:float, data:float -class CondMovFPFP fmt, bits<1> tf, - string instr_asm> : - FFCMOV { - let cc = 0; - let Uses = [FCR31]; - let Constraints = "$F = $fd"; -} - class CMov_I_F_FT : InstSE<(outs DRC:$fd), (ins DRC:$fs, CRC:$rt, DRC:$F), @@ -63,6 +32,7 @@ class CMov_I_F_FT : InstSE<(outs RC:$rd), (ins RC:$rs, RC:$F), @@ -72,6 +42,7 @@ class CMov_F_I_FT : InstSE<(outs RC:$fd), (ins RC:$fs, RC:$F), diff --git a/lib/Target/Mips/MipsInstrFPU.td b/lib/Target/Mips/MipsInstrFPU.td index 8354a9da35..3abc986ab3 100644 --- a/lib/Target/Mips/MipsInstrFPU.td +++ b/lib/Target/Mips/MipsInstrFPU.td @@ -86,102 +86,6 @@ def fpimm0neg : PatLeaf<(fpimm), [{ // Only S32 and D32 are supported right now. //===----------------------------------------------------------------------===// -// FP unary instructions without patterns. -class FFR1 funct, bits<5> fmt, string opstr, RegisterClass DstRC, - RegisterClass SrcRC> : - FFR<0x11, funct, fmt, (outs DstRC:$fd), (ins SrcRC:$fs), - !strconcat(opstr, "\t$fd, $fs"), []> { - let ft = 0; -} - -// FP unary instructions with patterns. -class FFR1P funct, bits<5> fmt, string opstr, RegisterClass DstRC, - RegisterClass SrcRC, SDNode OpNode> : - FFR<0x11, funct, fmt, (outs DstRC:$fd), (ins SrcRC:$fs), - !strconcat(opstr, "\t$fd, $fs"), - [(set DstRC:$fd, (OpNode SrcRC:$fs))]> { - let ft = 0; -} - -class FFR2P funct, bits<5> fmt, string opstr, RegisterClass RC, - SDNode OpNode> : - FFR<0x11, funct, fmt, (outs RC:$fd), (ins RC:$fs, RC:$ft), - !strconcat(opstr, "\t$fd, $fs, $ft"), - [(set RC:$fd, (OpNode RC:$fs, RC:$ft))]>; - -// FP load. -let DecoderMethod = "DecodeFMem" in { -class FPLoad op, string opstr, RegisterClass RC, Operand MemOpnd>: - FMem; - -// FP store. -class FPStore op, string opstr, RegisterClass RC, Operand MemOpnd>: - FMem; -} -// FP indexed load. -class FPIdxLoad funct, string opstr, RegisterClass DRC, - RegisterClass PRC, SDPatternOperator FOp = null_frag>: - FFMemIdx { - let fs = 0; -} - -// FP indexed store. -class FPIdxStore funct, string opstr, RegisterClass DRC, - RegisterClass PRC, SDPatternOperator FOp= null_frag>: - FFMemIdx { - let fd = 0; -} - -// Instructions that convert an FP value to 32-bit fixed point. -multiclass FFR1_W_M funct, string opstr> { - def _D32 : FFR1, - Requires<[NotFP64bit, HasStdEnc]>; - def _D64 : FFR1, - Requires<[IsFP64bit, HasStdEnc]> { - let DecoderNamespace = "Mips64"; - } -} - -// FP-to-FP conversion instructions. -multiclass FFR1P_M funct, string opstr, SDNode OpNode> { - def _D32 : FFR1P, - Requires<[NotFP64bit, HasStdEnc]>; - def _D64 : FFR1P, - Requires<[IsFP64bit, HasStdEnc]> { - let DecoderNamespace = "Mips64"; - } -} - -multiclass FFR2P_M funct, string opstr, SDNode OpNode> { - def _D32 : FFR2P, - Requires<[NotFP64bit, HasStdEnc]>; - def _D64 : FFR2P, - Requires<[IsFP64bit, HasStdEnc]> { - let DecoderNamespace = "Mips64"; - } -} - -// FP madd/msub/nmadd/nmsub instruction classes. -class FMADDSUB funct, bits<3> fmt, string opstr, - SDNode OpNode, RegisterClass RC> : - FFMADDSUB; - -class FNMADDSUB funct, bits<3> fmt, string opstr, - SDNode OpNode, RegisterClass RC> : - FFMADDSUB; - class ADDS_FT : InstSE<(outs RC:$fd), (ins RC:$fs, RC:$ft), @@ -360,13 +264,6 @@ defm FSQRT : ABSS_M<"sqrt.d", IIFsqrtDouble, fsqrt>, ABSS_FM<0x4, 17>; // When defining instructions, we reference all 32-bit registers, // regardless of register aliasing. -class FFRGPR _fmt, dag outs, dag ins, string asmstr, list pattern>: - FFR<0x11, 0x0, _fmt, outs, ins, asmstr, pattern> { - bits<5> rt; - let ft = rt; - let fd = 0; -} - /// Move Control Registers From/To CPU Registers def CFC1 : MFC1_FT<"cfc1", CPURegs, CCR, IIFmove>, MFC1_FM<2>; def CTC1 : MTC1_FT<"ctc1", CCR, CPURegs, IIFmove>, MFC1_FM<6>; @@ -503,16 +400,6 @@ let Predicates = [HasMips32r2, IsFP64bit, NoNaNsFPMath, HasStdEnc], def MIPS_BRANCH_F : PatLeaf<(i32 0)>; def MIPS_BRANCH_T : PatLeaf<(i32 1)>; -/// Floating Point Branch of False/True (Likely) -let isBranch=1, isTerminator=1, hasDelaySlot=1, base=0x8, Uses=[FCR31] in - class FBRANCH nd, bits<1> tf, PatLeaf op, string asmstr> : - FFI<0x11, (outs), (ins brtarget:$dst), !strconcat(asmstr, "\t$dst"), - [(MipsFPBrcond op, bb:$dst)]> { - let Inst{20-18} = 0; - let Inst{17} = nd; - let Inst{16} = tf; -} - let DecoderMethod = "DecodeBC1" in { def BC1F : BC1F_FT<"bc1f", IIBranch, MIPS_BRANCH_F>, BC1F_FM<0, 0>; def BC1T : BC1F_FT<"bc1t", IIBranch, MIPS_BRANCH_T>, BC1F_FM<0, 1>; @@ -539,11 +426,6 @@ def MIPS_FCOND_NGE : PatLeaf<(i32 13)>; def MIPS_FCOND_LE : PatLeaf<(i32 14)>; def MIPS_FCOND_NGT : PatLeaf<(i32 15)>; -class FCMP fmt, RegisterClass RC, string typestr> : - FCC; - /// Floating Point Compare def FCMP_S32 : CEQS_FT<"s", FGR32, IIFcmp, MipsFPCmp>, CEQS_FM<16>; def FCMP_D32 : CEQS_FT<"d", AFGR64, IIFcmp, MipsFPCmp>, CEQS_FM<17>, diff --git a/lib/Target/Mips/MipsInstrFormats.td b/lib/Target/Mips/MipsInstrFormats.td index e4d0a2067f..986580bf9f 100644 --- a/lib/Target/Mips/MipsInstrFormats.td +++ b/lib/Target/Mips/MipsInstrFormats.td @@ -205,31 +205,6 @@ class MFC3OP op, bits<5> _mfmt, dag outs, dag ins, string asmstr>: // //===----------------------------------------------------------------------===// -//===----------------------------------------------------------------------===// -// Format FR instruction class in Mips : <|opcode|fmt|ft|fs|fd|funct|> -//===----------------------------------------------------------------------===// - -class FFR op, bits<6> _funct, bits<5> _fmt, dag outs, dag ins, - string asmstr, list pattern> : - InstSE -{ - bits<5> fd; - bits<5> fs; - bits<5> ft; - bits<5> fmt; - bits<6> funct; - - let Opcode = op; - let funct = _funct; - let fmt = _fmt; - - let Inst{25-21} = fmt; - let Inst{20-16} = ft; - let Inst{15-11} = fs; - let Inst{10-6} = fd; - let Inst{5-0} = funct; -} - //===----------------------------------------------------------------------===// // Format FI instruction class in Mips : <|opcode|base|ft|immediate|> //===----------------------------------------------------------------------===// @@ -248,111 +223,6 @@ class FFI op, dag outs, dag ins, string asmstr, list pattern>: let Inst{15-0} = imm16; } -//===----------------------------------------------------------------------===// -// Compare instruction class in Mips : <|010001|fmt|ft|fs|0000011|condcode|> -//===----------------------------------------------------------------------===// - -class FCC _fmt, dag outs, dag ins, string asmstr, list pattern> : - InstSE -{ - bits<5> fs; - bits<5> ft; - bits<4> cc; - bits<5> fmt; - - let Opcode = 0x11; - let fmt = _fmt; - - let Inst{25-21} = fmt; - let Inst{20-16} = ft; - let Inst{15-11} = fs; - let Inst{10-6} = 0; - let Inst{5-4} = 0b11; - let Inst{3-0} = cc; -} - - -class FCMOV _tf, dag outs, dag ins, string asmstr, - list pattern> : - InstSE -{ - bits<5> rd; - bits<5> rs; - bits<3> cc; - bits<1> tf; - - let Opcode = 0; - let tf = _tf; - - let Inst{25-21} = rs; - let Inst{20-18} = cc; - let Inst{17} = 0; - let Inst{16} = tf; - let Inst{15-11} = rd; - let Inst{10-6} = 0; - let Inst{5-0} = 1; -} - -class FFCMOV _fmt, bits<1> _tf, dag outs, dag ins, string asmstr, - list pattern> : - InstSE -{ - bits<5> fd; - bits<5> fs; - bits<3> cc; - bits<5> fmt; - bits<1> tf; - - let Opcode = 17; - let fmt = _fmt; - let tf = _tf; - - let Inst{25-21} = fmt; - let Inst{20-18} = cc; - let Inst{17} = 0; - let Inst{16} = tf; - let Inst{15-11} = fs; - let Inst{10-6} = fd; - let Inst{5-0} = 17; -} - -// Floating point madd/msub/nmadd/nmsub. -class FFMADDSUB funct, bits<3> fmt, dag outs, dag ins, string asmstr, - list pattern> - : InstSE { - bits<5> fd; - bits<5> fr; - bits<5> fs; - bits<5> ft; - - let Opcode = 0x13; - let Inst{25-21} = fr; - let Inst{20-16} = ft; - let Inst{15-11} = fs; - let Inst{10-6} = fd; - let Inst{5-3} = funct; - let Inst{2-0} = fmt; -} - -// FP indexed load/store instructions. -class FFMemIdx funct, dag outs, dag ins, string asmstr, - list pattern> : - InstSE -{ - bits<5> base; - bits<5> index; - bits<5> fs; - bits<5> fd; - - let Opcode = 0x13; - - let Inst{25-21} = base; - let Inst{20-16} = index; - let Inst{15-11} = fs; - let Inst{10-6} = fd; - let Inst{5-0} = funct; -} - class ADDS_FM funct, bits<5> fmt> { bits<5> fd; bits<5> fs; -- cgit v1.2.3