From dc2f79274021a590d6b72acd741117068c3e49bd Mon Sep 17 00:00:00 2001 From: Akira Hatanaka Date: Fri, 15 Feb 2013 21:20:45 +0000 Subject: [mips] Split SelectAddr, which was used to match address patterns, into two functions. Set AddedComplexity to determine the order in which patterns are matched. This simplifies selection of floating point loads/stores. No functionality change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175300 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Mips/MipsISelDAGToDAG.cpp | 39 ++++++++++++++++++++++----------- lib/Target/Mips/MipsInstrFPU.td | 42 ++++++++++++++++++++++++++++++++---- lib/Target/Mips/MipsInstrInfo.td | 8 ++++++- 3 files changed, 71 insertions(+), 18 deletions(-) diff --git a/lib/Target/Mips/MipsISelDAGToDAG.cpp b/lib/Target/Mips/MipsISelDAGToDAG.cpp index c5f12907d9..385ade5b2a 100644 --- a/lib/Target/Mips/MipsISelDAGToDAG.cpp +++ b/lib/Target/Mips/MipsISelDAGToDAG.cpp @@ -96,7 +96,17 @@ private: SDNode *Select(SDNode *N); // Complex Pattern. - bool SelectAddr(SDNode *Parent, SDValue N, SDValue &Base, SDValue &Offset); + /// (reg + imm). + bool selectAddrRegImm(SDNode *Parent, SDValue Addr, SDValue &Base, + SDValue &Offset) const; + + /// Fall back on this function if all else fails. + bool selectAddrDefault(SDNode *Parent, SDValue Addr, SDValue &Base, + SDValue &Offset) const; + + /// Match integer address pattern. + bool selectIntAddr(SDNode *Parent, SDValue Addr, SDValue &Base, + SDValue &Offset) const; bool SelectAddr16(SDNode *Parent, SDValue N, SDValue &Base, SDValue &Offset, SDValue &Alias); @@ -323,8 +333,8 @@ SDValue MipsDAGToDAGISel::getMips16SPAliasReg() { /// ComplexPattern used on MipsInstrInfo /// Used on Mips Load/Store instructions -bool MipsDAGToDAGISel:: -SelectAddr(SDNode *Parent, SDValue Addr, SDValue &Base, SDValue &Offset) { +bool MipsDAGToDAGISel::selectAddrRegImm(SDNode *Parent, SDValue Addr, + SDValue &Base, SDValue &Offset) const { EVT ValTy = Addr.getValueType(); // if Address is FI, get the TargetFrameIndex. @@ -384,21 +394,24 @@ SelectAddr(SDNode *Parent, SDValue Addr, SDValue &Base, SDValue &Offset) { return true; } } - - // If an indexed floating point load/store can be emitted, return false. - const LSBaseSDNode *LS = dyn_cast(Parent); - - if (LS && - (LS->getMemoryVT() == MVT::f32 || LS->getMemoryVT() == MVT::f64) && - Subtarget.hasFPIdx()) - return false; } - Base = Addr; - Offset = CurDAG->getTargetConstant(0, ValTy); + return false; +} + +bool MipsDAGToDAGISel::selectAddrDefault(SDNode *Parent, SDValue Addr, + SDValue &Base, SDValue &Offset) const { + Base = Addr; + Offset = CurDAG->getTargetConstant(0, Addr.getValueType()); return true; } +bool MipsDAGToDAGISel::selectIntAddr(SDNode *Parent, SDValue Addr, + SDValue &Base, SDValue &Offset) const { + return selectAddrRegImm(Parent, Addr, Base, Offset) || + selectAddrDefault(Parent, Addr, Base, Offset); +} + void MipsDAGToDAGISel::getMips16SPRefReg(SDNode *Parent, SDValue &AliasReg) { SDValue AliasFPReg = CurDAG->getRegister(Mips::S0, TLI.getPointerTy()); if (Parent) { diff --git a/lib/Target/Mips/MipsInstrFPU.td b/lib/Target/Mips/MipsInstrFPU.td index 70465d86ca..891bdc1224 100644 --- a/lib/Target/Mips/MipsInstrFPU.td +++ b/lib/Target/Mips/MipsInstrFPU.td @@ -152,14 +152,14 @@ class MTC1_FT_CCR : InstSE<(outs RC:$rt), (ins MemOpnd:$addr), !strconcat(opstr, "\t$rt, $addr"), - [(set RC:$rt, (OpNode addr:$addr))], Itin, FrmFI> { + [(set RC:$rt, (OpNode addrDefault:$addr))], Itin, FrmFI> { let DecoderMethod = "DecodeFMem"; } class SW_FT : InstSE<(outs), (ins RC:$rt, MemOpnd:$addr), !strconcat(opstr, "\t$rt, $addr"), - [(OpNode RC:$rt, addr:$addr)], Itin, FrmFI> { + [(OpNode RC:$rt, addrDefault:$addr)], Itin, FrmFI> { let DecoderMethod = "DecodeFMem"; } @@ -180,13 +180,17 @@ class LWXC1_FT : InstSE<(outs DRC:$fd), (ins PRC:$base, PRC:$index), !strconcat(opstr, "\t$fd, ${index}(${base})"), - [(set DRC:$fd, (OpNode (add PRC:$base, PRC:$index)))], Itin, FrmFI>; + [(set DRC:$fd, (OpNode (add PRC:$base, PRC:$index)))], Itin, FrmFI> { + let AddedComplexity = 20; +} class SWXC1_FT : InstSE<(outs), (ins DRC:$fs, PRC:$base, PRC:$index), !strconcat(opstr, "\t$fs, ${index}(${base})"), - [(OpNode DRC:$fs, (add PRC:$base, PRC:$index))], Itin, FrmFI>; + [(OpNode DRC:$fs, (add PRC:$base, PRC:$index))], Itin, FrmFI> { + let AddedComplexity = 20; +} class BC1F_FT : @@ -498,3 +502,33 @@ let Predicates = [IsFP64bit, HasStdEnc] in { def : MipsPat<(f32 (fround FGR64:$src)), (CVT_S_D64 FGR64:$src)>; def : MipsPat<(f64 (fextend FGR32:$src)), (CVT_D64_S FGR32:$src)>; } + +// Load/Store patterns. +let AddedComplexity = 40 in { + let Predicates = [IsN64, HasStdEnc] in { + def : MipsPat<(f32 (load addrRegImm:$a)), (LWC1_P8 addrRegImm:$a)>; + def : MipsPat<(store FGR32:$v, addrRegImm:$a), + (SWC1_P8 FGR32:$v, addrRegImm:$a)>; + def : MipsPat<(f64 (load addrRegImm:$a)), (LDC164_P8 addrRegImm:$a)>; + def : MipsPat<(store FGR64:$v, addrRegImm:$a), + (SDC164_P8 FGR64:$v, addrRegImm:$a)>; + } + + let Predicates = [NotN64, HasStdEnc] in { + def : MipsPat<(f32 (load addrRegImm:$a)), (LWC1 addrRegImm:$a)>; + def : MipsPat<(store FGR32:$v, addrRegImm:$a), + (SWC1 FGR32:$v, addrRegImm:$a)>; + } + + let Predicates = [NotN64, HasMips64, HasStdEnc] in { + def : MipsPat<(f64 (load addrRegImm:$a)), (LDC164 addrRegImm:$a)>; + def : MipsPat<(store FGR64:$v, addrRegImm:$a), + (SDC164 FGR64:$v, addrRegImm:$a)>; + } + + let Predicates = [NotN64, NotMips64, HasStdEnc] in { + def : MipsPat<(f64 (load addrRegImm:$a)), (LDC1 addrRegImm:$a)>; + def : MipsPat<(store AFGR64:$v, addrRegImm:$a), + (SDC1 AFGR64:$v, addrRegImm:$a)>; + } +} diff --git a/lib/Target/Mips/MipsInstrInfo.td b/lib/Target/Mips/MipsInstrInfo.td index 052e855031..f37f9352c1 100644 --- a/lib/Target/Mips/MipsInstrInfo.td +++ b/lib/Target/Mips/MipsInstrInfo.td @@ -334,7 +334,13 @@ def immZExt5 : ImmLeaf; // Mips Address Mode! SDNode frameindex could possibily be a match // since load and store instructions from stack used it. def addr : - ComplexPattern; + ComplexPattern; + +def addrRegImm : + ComplexPattern; + +def addrDefault : + ComplexPattern; //===----------------------------------------------------------------------===// // Instructions specific format -- cgit v1.2.3