From dd6669dbb872a69a42a0d8fd77cd48a971cabcc9 Mon Sep 17 00:00:00 2001 From: Bill Wendling Date: Mon, 9 Dec 2013 02:58:56 +0000 Subject: Merging r196724: ------------------------------------------------------------------------ r196724 | tnorthover | 2013-12-08 07:24:55 -0800 (Sun, 08 Dec 2013) | 5 lines ARM: teach Sema that "r" can match 64-bit values We already support using "r" on 64-bit values (a GPRPair is allocated), but Sema doesn't know this yet so issues a warning. This should fix it. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/cfe/branches/release_34@196746 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Basic/Targets.cpp | 2 +- test/Sema/arm-asm.c | 5 +++++ 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/lib/Basic/Targets.cpp b/lib/Basic/Targets.cpp index 4244edfbee..bccd0d72d8 100644 --- a/lib/Basic/Targets.cpp +++ b/lib/Basic/Targets.cpp @@ -4106,7 +4106,7 @@ public: case 'r': { switch (Modifier) { default: - return (isInOut || isOutput || Size <= 32); + return (isInOut || isOutput || Size <= 64); case 'q': // A register of size 32 cannot fit a vector type. return false; diff --git a/test/Sema/arm-asm.c b/test/Sema/arm-asm.c index 3fc0eeb754..e48718b0a2 100644 --- a/test/Sema/arm-asm.c +++ b/test/Sema/arm-asm.c @@ -5,3 +5,8 @@ void f (void) { asm volatile ("lw (r1), %0[val]": "=&b"(Val)); // expected-error {{invalid output constraint '=&b' in asm}} return; } + +void test_64bit_r(void) { + long long foo = 0, bar = 0; + asm volatile("INST %0, %1" : "=r"(foo) : "r"(bar)); +} -- cgit v1.2.3