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| author | Bill Wendling <isanbard@gmail.com> | 2013-05-16 00:27:42 +0000 |
|---|---|---|
| committer | Bill Wendling <isanbard@gmail.com> | 2013-05-16 00:27:42 +0000 |
| commit | 91310e4a3021431fe84805ec2eeeaa938526c9e3 (patch) | |
| tree | 2c129d72094714783cb630fd9cfcac9c8ac96660 | |
| parent | 3e17699c38f88b84f24f6fe3bd92164059ed49e4 (diff) | |
| download | llvm-91310e4a3021431fe84805ec2eeeaa938526c9e3.tar.gz llvm-91310e4a3021431fe84805ec2eeeaa938526c9e3.tar.bz2 llvm-91310e4a3021431fe84805ec2eeeaa938526c9e3.tar.xz | |
Merging r181579:
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r181579 | tstellar | 2013-05-09 19:09:39 -0700 (Thu, 09 May 2013) | 8 lines
R600: Expand SUB for v2i32/v4i32
Patch by: Aaron Watry
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Signed-off-by: Aaron Watry <awatry@gmail.com>
NOTE: This is a candidate for the 3.3 branch.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_33@181953 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/R600/R600ISelLowering.cpp | 2 | ||||
| -rw-r--r-- | test/CodeGen/R600/sub.ll | 15 |
2 files changed, 17 insertions, 0 deletions
diff --git a/lib/Target/R600/R600ISelLowering.cpp b/lib/Target/R600/R600ISelLowering.cpp index b9822799e7..7252235d5b 100644 --- a/lib/Target/R600/R600ISelLowering.cpp +++ b/lib/Target/R600/R600ISelLowering.cpp @@ -54,6 +54,8 @@ R600TargetLowering::R600TargetLowering(TargetMachine &TM) : setOperationAction(ISD::SRL, MVT::v2i32, Expand); setOperationAction(ISD::SRA, MVT::v4i32, Expand); setOperationAction(ISD::SRA, MVT::v2i32, Expand); + setOperationAction(ISD::SUB, MVT::v4i32, Expand); + setOperationAction(ISD::SUB, MVT::v2i32, Expand); setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Expand); setOperationAction(ISD::UDIV, MVT::v4i32, Expand); setOperationAction(ISD::UREM, MVT::v4i32, Expand); diff --git a/test/CodeGen/R600/sub.ll b/test/CodeGen/R600/sub.ll new file mode 100644 index 0000000000..12bfba3975 --- /dev/null +++ b/test/CodeGen/R600/sub.ll @@ -0,0 +1,15 @@ +;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s + +;CHECK: SUB_INT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +;CHECK: SUB_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +;CHECK: SUB_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +;CHECK: SUB_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} + +define void @test(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) { + %b_ptr = getelementptr <4 x i32> addrspace(1)* %in, i32 1 + %a = load <4 x i32> addrspace(1) * %in + %b = load <4 x i32> addrspace(1) * %b_ptr + %result = sub <4 x i32> %a, %b + store <4 x i32> %result, <4 x i32> addrspace(1)* %out + ret void +} |