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author | Chris Lattner <sabre@nondot.org> | 2010-10-01 05:36:09 +0000 |
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committer | Chris Lattner <sabre@nondot.org> | 2010-10-01 05:36:09 +0000 |
commit | 2831a194954cb4a79049e8a666d246a9a1662b92 (patch) | |
tree | a98de897356d328fa2e8a939ace0f2673abec9bc | |
parent | b0ab5d04dd2e253fa2504208ebb1bfafa3d8a018 (diff) | |
download | llvm-2831a194954cb4a79049e8a666d246a9a1662b92.tar.gz llvm-2831a194954cb4a79049e8a666d246a9a1662b92.tar.bz2 llvm-2831a194954cb4a79049e8a666d246a9a1662b92.tar.xz |
fix rdar://8494845 + PR8244 - a miscompile exposed by my patch in r101350
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115294 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r-- | lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 9 | ||||
-rw-r--r-- | test/CodeGen/X86/shift-folding.ll | 6 | ||||
-rw-r--r-- | test/CodeGen/X86/store-narrow.ll | 14 |
3 files changed, 26 insertions, 3 deletions
diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index be95c08e2f..ede54e5ed2 100644 --- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -4087,6 +4087,15 @@ SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) { if ((N0.getValueType().getSizeInBits() & (EVTBits-1)) != 0) return SDValue(); } + + // If the shift amount is larger than the input type then we're not + // accessing any of the loaded bytes. If the load was a zextload/extload + // then the result of the shift+trunc is zero/undef (handled elsewhere). + // If the load was a sextload then the result is a splat of the sign bit + // of the extended byte. This is not worth optimizing for. + if (ShAmt >= VT.getSizeInBits()) + return SDValue(); + } } diff --git a/test/CodeGen/X86/shift-folding.ll b/test/CodeGen/X86/shift-folding.ll index 48ca36ca98..d9c3061ff6 100644 --- a/test/CodeGen/X86/shift-folding.ll +++ b/test/CodeGen/X86/shift-folding.ll @@ -1,21 +1,21 @@ ; RUN: llc < %s -march=x86 | \ ; RUN: grep {s\[ah\]\[rl\]l} | count 1 -define i32* @test1(i32* %P, i32 %X) { +define i32* @test1(i32* %P, i32 %X) nounwind { %Y = lshr i32 %X, 2 ; <i32> [#uses=1] %gep.upgrd.1 = zext i32 %Y to i64 ; <i64> [#uses=1] %P2 = getelementptr i32* %P, i64 %gep.upgrd.1 ; <i32*> [#uses=1] ret i32* %P2 } -define i32* @test2(i32* %P, i32 %X) { +define i32* @test2(i32* %P, i32 %X) nounwind { %Y = shl i32 %X, 2 ; <i32> [#uses=1] %gep.upgrd.2 = zext i32 %Y to i64 ; <i64> [#uses=1] %P2 = getelementptr i32* %P, i64 %gep.upgrd.2 ; <i32*> [#uses=1] ret i32* %P2 } -define i32* @test3(i32* %P, i32 %X) { +define i32* @test3(i32* %P, i32 %X) nounwind { %Y = ashr i32 %X, 2 ; <i32> [#uses=1] %P2 = getelementptr i32* %P, i32 %Y ; <i32*> [#uses=1] ret i32* %P2 diff --git a/test/CodeGen/X86/store-narrow.ll b/test/CodeGen/X86/store-narrow.ll index abc5174c98..0dd228eb14 100644 --- a/test/CodeGen/X86/store-narrow.ll +++ b/test/CodeGen/X86/store-narrow.ll @@ -152,3 +152,17 @@ define void @test9() nounwind { store i32 %or, i32* @g_16 ret void } + +; rdar://8494845 + PR8244 +; X64: test10: +; X64-NEXT: movsbl (%rdi), %eax +; X64-NEXT: shrl $8, %eax +; X64-NEXT: ret +define i8 @test10(i8* %P) nounwind ssp { +entry: + %tmp = load i8* %P, align 1 + %conv = sext i8 %tmp to i32 + %shr3 = lshr i32 %conv, 8 + %conv2 = trunc i32 %shr3 to i8 + ret i8 %conv2 +} |