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author | Nadav Rotem <nadav.rotem@intel.com> | 2011-12-08 13:10:01 +0000 |
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committer | Nadav Rotem <nadav.rotem@intel.com> | 2011-12-08 13:10:01 +0000 |
commit | 44bac7cd659090f15face5171e3c346983aeb521 (patch) | |
tree | 5e99d7ec6f06d3210a866aae8cdf8759368a13a1 | |
parent | 72590c973837f7d56638feb511a79574391f0eac (diff) | |
download | llvm-44bac7cd659090f15face5171e3c346983aeb521.tar.gz llvm-44bac7cd659090f15face5171e3c346983aeb521.tar.bz2 llvm-44bac7cd659090f15face5171e3c346983aeb521.tar.xz |
Fix a bug in the integer-promotion of bitcast operations on vector types.
We must not issue a bitcast operation for integer-promotion of vector types, because the
location of the values in the vector may be different.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146150 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r-- | lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp | 2 | ||||
-rw-r--r-- | test/CodeGen/X86/2011-12-8-bitcastintprom.ll | 15 | ||||
-rw-r--r-- | test/CodeGen/X86/vec_compare-2.ll | 1 | ||||
-rw-r--r-- | test/CodeGen/X86/widen_arith-3.ll | 2 |
4 files changed, 18 insertions, 2 deletions
diff --git a/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp b/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp index fd24238a91..a48ee7efdc 100644 --- a/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp +++ b/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp @@ -216,7 +216,7 @@ SDValue DAGTypeLegalizer::PromoteIntRes_BITCAST(SDNode *N) { case TargetLowering::TypeLegal: break; case TargetLowering::TypePromoteInteger: - if (NOutVT.bitsEq(NInVT)) + if (NOutVT.bitsEq(NInVT) && !NOutVT.isVector() && !NInVT.isVector()) // The input promotes to the same size. Convert the promoted value. return DAG.getNode(ISD::BITCAST, dl, NOutVT, GetPromotedInteger(InOp)); break; diff --git a/test/CodeGen/X86/2011-12-8-bitcastintprom.ll b/test/CodeGen/X86/2011-12-8-bitcastintprom.ll new file mode 100644 index 0000000000..ceee8e6041 --- /dev/null +++ b/test/CodeGen/X86/2011-12-8-bitcastintprom.ll @@ -0,0 +1,15 @@ +; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7 | FileCheck %s + +; Make sure that the conversion between v4i8 to v2i16 is not a simple bitcast. +; CHECK: prom_bug +; CHECK: movd +; CHECK: shufb +; CHECK: movw +; CHECK: ret +define void @prom_bug(<4 x i8> %t, i16* %p) { + %r = bitcast <4 x i8> %t to <2 x i16> + %o = extractelement <2 x i16> %r, i32 0 + store i16 %o, i16* %p + ret void +} + diff --git a/test/CodeGen/X86/vec_compare-2.ll b/test/CodeGen/X86/vec_compare-2.ll index 04bb7254fb..aaa585b35f 100644 --- a/test/CodeGen/X86/vec_compare-2.ll +++ b/test/CodeGen/X86/vec_compare-2.ll @@ -8,6 +8,7 @@ declare <4 x i32> @llvm.x86.sse41.pmaxsd(<4 x i32>, <4 x i32>) nounwind readnone define void @blackDespeckle_wrapper(i8** %args_list, i64* %gtid, i64 %xend) { entry: +; CHECK: cfi_def_cfa_offset ; CHECK-NOT: set ; CHECK: pcmpgt ; CHECK: blendvps diff --git a/test/CodeGen/X86/widen_arith-3.ll b/test/CodeGen/X86/widen_arith-3.ll index 11d56f5786..b959ce82c9 100644 --- a/test/CodeGen/X86/widen_arith-3.ll +++ b/test/CodeGen/X86/widen_arith-3.ll @@ -1,5 +1,5 @@ ; RUN: llc < %s -march=x86 -mattr=+sse42 -post-RA-scheduler=true | FileCheck %s -; CHECK: incw +; CHECK: incl ; CHECK: incl ; CHECK: incl ; CHECK: addl |