Require non-NULL register masks.

It doesn't seem worthwhile to give meaning to a NULL register mask
pointer. It complicates all the code using register mask operands.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149646 91177308-0d34-0410-b5e6-96231b3b80d8

6 files changed, 12 insertions, 15 deletions

diff --git a/include/llvm/CodeGen/MachineOperand.h b/include/llvm/CodeGen/MachineOperand.h
index 6a2e38dd84..59da26c71c 100644
--- a/include/llvm/CodeGen/MachineOperand.h
+++ b/include/llvm/CodeGen/MachineOperand.h
@@ -446,12 +446,11 @@ public:
     assert(isRegMask() && "Wrong MachineOperand accessor");
     // See TargetRegisterInfo.h.
     assert(PhysReg < (1u << 30) && "Not a physical register");
-    return !Contents.RegMask ||
-           !(Contents.RegMask[PhysReg / 32] & (1u << PhysReg % 32));
+    return !(Contents.RegMask[PhysReg / 32] & (1u << PhysReg % 32));
   }
 
   /// getRegMask - Returns a bit mask of registers preserved by this RegMask
-  /// operand.  A NULL pointer means that all registers are clobbered.
+  /// operand.
   const uint32_t *getRegMask() const {
     assert(isRegMask() && "Wrong MachineOperand accessor");
     return Contents.RegMask;
@@ -616,6 +615,7 @@ public:
   /// Any physreg with a 0 bit in the mask is clobbered by the instruction.
   ///
   static MachineOperand CreateRegMask(const uint32_t *Mask) {
+    assert(Mask && "Missing register mask");
     MachineOperand Op(MachineOperand::MO_RegisterMask);
     Op.Contents.RegMask = Mask;
     return Op;
diff --git a/include/llvm/Target/TargetRegisterInfo.h b/include/llvm/Target/TargetRegisterInfo.h
index 36ac5df120..711129f833 100644
--- a/include/llvm/Target/TargetRegisterInfo.h
+++ b/include/llvm/Target/TargetRegisterInfo.h
@@ -376,7 +376,10 @@ public:
   ///
   /// Bits are numbered from the LSB, so the bit for physical register Reg can
   /// be found as (Mask[Reg / 32] >> Reg % 32) & 1.
-  /// NULL pointer is equivalent to an all-zero mask.
+  ///
+  /// A NULL pointer means that no register mask will be used, and call
+  /// instructions should use implicit-def operands to indicate call clobbered
+  /// registers.
   ///
   virtual const uint32_t *getCallPreservedMask(CallingConv::ID) const {
     // The default mask clobbers everything.  All targets should override.
diff --git a/lib/CodeGen/DeadMachineInstructionElim.cpp b/lib/CodeGen/DeadMachineInstructionElim.cpp
index aeb0b3ed02..020b64d883 100644
--- a/lib/CodeGen/DeadMachineInstructionElim.cpp
+++ b/lib/CodeGen/DeadMachineInstructionElim.cpp
@@ -175,10 +175,7 @@ bool DeadMachineInstructionElim::runOnMachineFunction(MachineFunction &MF) {
           }
         } else if (MO.isRegMask()) {
           // Register mask of preserved registers. All clobbers are dead.
-          if (const uint32_t *Mask = MO.getRegMask())
-            LivePhysRegs.clearBitsNotInMask(Mask);
-          else
-            LivePhysRegs.reset();
+          LivePhysRegs.clearBitsNotInMask(MO.getRegMask());
           LivePhysRegs |= ReservedRegs;
         }
       }
diff --git a/lib/CodeGen/MachineInstr.cpp b/lib/CodeGen/MachineInstr.cpp
index c281cd1149..7cf282c25c 100644
--- a/lib/CodeGen/MachineInstr.cpp
+++ b/lib/CodeGen/MachineInstr.cpp
@@ -327,7 +327,7 @@ void MachineOperand::print(raw_ostream &OS, const TargetMachine *TM) const {
     OS << '>';
     break;
   case MachineOperand::MO_RegisterMask:
-    OS << (getRegMask() ? "<regmask>" : "<regmask:null>");
+    OS << "<regmask>";
     break;
   case MachineOperand::MO_Metadata:
     OS << '<';
diff --git a/lib/CodeGen/MachineLICM.cpp b/lib/CodeGen/MachineLICM.cpp
index 49a109e252..9b058c3416 100644
--- a/lib/CodeGen/MachineLICM.cpp
+++ b/lib/CodeGen/MachineLICM.cpp
@@ -417,10 +417,7 @@ void MachineLICM::ProcessMI(MachineInstr *MI,
     // We can't hoist an instruction defining a physreg that is clobbered in
     // the loop.
     if (MO.isRegMask()) {
-      if (const uint32_t *Mask = MO.getRegMask())
-        PhysRegClobbers.setBitsNotInMask(Mask);
-      else
-        PhysRegClobbers.set();
+      PhysRegClobbers.setBitsNotInMask(MO.getRegMask());
       continue;
     }
 
diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index 5d99a1c7d8..05c0ebd5ca 100644
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -2515,8 +2515,8 @@ X86TargetLowering::LowerCall(SDValue Chain, SDValue Callee,
   // registers.
   if (UseRegMask) {
     const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
-    const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
-    Ops.push_back(DAG.getRegisterMask(Mask));
+    if (const uint32_t *Mask = TRI->getCallPreservedMask(CallConv))
+      Ops.push_back(DAG.getRegisterMask(Mask));
   }
 
   if (InFlag.getNode())