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| author | Amaury de la Vieuville <amaury.dlv@gmail.com> | 2013-06-24 09:11:53 +0000 |
|---|---|---|
| committer | Amaury de la Vieuville <amaury.dlv@gmail.com> | 2013-06-24 09:11:53 +0000 |
| commit | 4ee72398a15cd7b8e217bb3d34a4e9e0e72caca1 (patch) | |
| tree | bd75f19bcaafd51f4a4e9b45d8c1d9c85226ffa3 | |
| parent | ff08da15cf3d0412ee9cc325fc5a720bcad178f2 (diff) | |
| download | llvm-4ee72398a15cd7b8e217bb3d34a4e9e0e72caca1.tar.gz llvm-4ee72398a15cd7b8e217bb3d34a4e9e0e72caca1.tar.bz2 llvm-4ee72398a15cd7b8e217bb3d34a4e9e0e72caca1.tar.xz | |
ARM: fix thumb1 nop decoding
In thumb1, NOP is a pseudo-instruction equivalent to mov r8, r8.
However the disassembler should not use this alias.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184703 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp | 9 | ||||
| -rw-r--r-- | test/MC/ARM/thumb-nop.s | 2 | ||||
| -rw-r--r-- | test/MC/ARM/thumb.s | 2 | ||||
| -rw-r--r-- | test/MC/Disassembler/ARM/thumb1.txt | 10 |
4 files changed, 4 insertions, 19 deletions
diff --git a/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp b/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp index 62394faa68..8734e44197 100644 --- a/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp +++ b/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp @@ -243,15 +243,6 @@ void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O, return; } - // Thumb1 NOP - if (Opcode == ARM::tMOVr && MI->getOperand(0).getReg() == ARM::R8 && - MI->getOperand(1).getReg() == ARM::R8) { - O << "\tnop"; - printPredicateOperand(MI, 2, O); - printAnnotation(O, Annot); - return; - } - // Combine 2 GPRs from disassember into a GPRPair to match with instr def. // ldrexd/strexd require even/odd GPR pair. To enforce this constraint, // a single GPRPair reg operand is used in the .td file to replace the two diff --git a/test/MC/ARM/thumb-nop.s b/test/MC/ARM/thumb-nop.s index 0b580ea14a..66f61a6e0b 100644 --- a/test/MC/ARM/thumb-nop.s +++ b/test/MC/ARM/thumb-nop.s @@ -5,5 +5,5 @@ nop -@ CHECK-V6: nop @ encoding: [0xc0,0x46] +@ CHECK-V6: mov r8, r8 @ encoding: [0xc0,0x46] @ CHECK-V7: nop @ encoding: [0x00,0xbf] diff --git a/test/MC/ARM/thumb.s b/test/MC/ARM/thumb.s index 2223bdcd46..9a725410c3 100644 --- a/test/MC/ARM/thumb.s +++ b/test/MC/ARM/thumb.s @@ -42,7 +42,7 @@ @ CHECK: bkpt #2 @ encoding: [0x02,0xbe] nop -@ CHECK: nop @ encoding: [0xc0,0x46] +@ CHECK: mov r8, r8 @ encoding: [0xc0,0x46] cpsie aif @ CHECK: cpsie aif @ encoding: [0x67,0xb6] diff --git a/test/MC/Disassembler/ARM/thumb1.txt b/test/MC/Disassembler/ARM/thumb1.txt index de9596aab7..7362d9b9b2 100644 --- a/test/MC/Disassembler/ARM/thumb1.txt +++ b/test/MC/Disassembler/ARM/thumb1.txt @@ -279,9 +279,11 @@ #------------------------------------------------------------------------------ # CHECK: mov r3, r4 # CHECK: movs r1, r3 +# CHECK: mov r8, r8 0x23 0x46 0x19 0x00 +0xc0 0x46 #------------------------------------------------------------------------------ @@ -310,14 +312,6 @@ #------------------------------------------------------------------------------ -# NOP -#------------------------------------------------------------------------------ -# CHECK: nop - -0xc0 0x46 - - -#------------------------------------------------------------------------------ # ORR #------------------------------------------------------------------------------ # CHECK: orrs r3, r4 |