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author | Shuxin Yang <shuxin.llvm@gmail.com> | 2012-12-12 00:29:03 +0000 |
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committer | Shuxin Yang <shuxin.llvm@gmail.com> | 2012-12-12 00:29:03 +0000 |
commit | 5f70c2e934c8cf7814fc047f4824ac89b35dd72d (patch) | |
tree | 3f4df3e7ca234645eda5b0d4143fb104a59016a1 | |
parent | c244f381768e2e6ab9daa807adbee18de4756a07 (diff) | |
download | llvm-5f70c2e934c8cf7814fc047f4824ac89b35dd72d.tar.gz llvm-5f70c2e934c8cf7814fc047f4824ac89b35dd72d.tar.bz2 llvm-5f70c2e934c8cf7814fc047f4824ac89b35dd72d.tar.xz |
- Fix a problematic way in creating all-the-1 APInt.
- Propagate "exact" bit of [l|a]shr instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169942 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r-- | lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp | 6 | ||||
-rw-r--r-- | test/Transforms/InstCombine/shift.ll | 10 |
2 files changed, 14 insertions, 2 deletions
diff --git a/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp b/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp index 08aedb3200..13653183a7 100644 --- a/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp +++ b/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp @@ -858,8 +858,8 @@ Value *InstCombiner::SimplifyShrShlDemandedBits(Instruction *Shr, Value *VarX = Shr->getOperand(0); Type *Ty = VarX->getType(); - APInt BitMask1(Ty->getIntegerBitWidth(), (uint64_t)-1); - APInt BitMask2(Ty->getIntegerBitWidth(), (uint64_t)-1); + APInt BitMask1(APInt::getAllOnesValue(Ty->getIntegerBitWidth())); + APInt BitMask2(APInt::getAllOnesValue(Ty->getIntegerBitWidth())); bool isLshr = (Shr->getOpcode() == Instruction::LShr); BitMask1 = isLshr ? (BitMask1.lshr(ShrAmt) << ShlAmt) : @@ -891,6 +891,8 @@ Value *InstCombiner::SimplifyShrShlDemandedBits(Instruction *Shr, Constant *Amt = ConstantInt::get(VarX->getType(), ShrAmt - ShlAmt); New = isLshr ? BinaryOperator::CreateLShr(VarX, Amt) : BinaryOperator::CreateAShr(VarX, Amt); + if (cast<BinaryOperator>(Shr)->isExact()) + New->setIsExact(true); } return InsertNewInstWith(New, *Shl); diff --git a/test/Transforms/InstCombine/shift.ll b/test/Transforms/InstCombine/shift.ll index 32867761a3..41f8aa9ee8 100644 --- a/test/Transforms/InstCombine/shift.ll +++ b/test/Transforms/InstCombine/shift.ll @@ -735,3 +735,13 @@ define i32 @test61(i32 %x) { ; CHECK: @test61 ; CHECK: ashr i32 %x, 4 } + +; propagate "exact" trait +define i32 @test62(i32 %x) { + %shr = ashr exact i32 %x, 4 + %shl = shl i32 %shr, 1 + %or = or i32 %shl, 1 + ret i32 %or +; CHECK: @test62 +; CHECK: ashr exact i32 %x, 3 +} |