Revert r191393 since it caused pr17380.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191438 91177308-0d34-0410-b5e6-96231b3b80d8

2 files changed, 0 insertions, 201 deletions

diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index dda35f65c2..d5f3e9c53e 100644
--- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -3748,26 +3748,6 @@ SDValue DAGCombiner::visitSHL(SDNode *N) {
     }
   }
 
-  // fold (shl (zext (srl x, C)), C) -> (zext (shl (srl x, C), C))
-  // Only fold this if the inner zext has no other uses to avoid increasing
-  // the total number of instructions.
-  if (N1C && N0.getOpcode() == ISD::ZERO_EXTEND && N0.hasOneUse() &&
-      N0.getOperand(0).getOpcode() == ISD::SRL &&
-      isa<ConstantSDNode>(N0.getOperand(0)->getOperand(1))) {
-    uint64_t c1 =
-      cast<ConstantSDNode>(N0.getOperand(0)->getOperand(1))->getZExtValue();
-    if (c1 < VT.getSizeInBits()) {
-      uint64_t c2 = N1C->getZExtValue();
-      if (c1 == c2) {
-        SDValue NewOp0 = N0.getOperand(0);
-        EVT ShiftVT = NewOp0.getValueType();
-        SDValue NewSHL = DAG.getNode(ISD::SHL, SDLoc(N), ShiftVT,
-                                     NewOp0, DAG.getConstant(c2, ShiftVT));
-        return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N0), VT, NewSHL);
-      }
-    }
-  }
-
   // fold (shl (srl x, c1), c2) -> (and (shl x, (sub c2, c1), MASK) or
   //                               (and (srl x, (sub c1, c2), MASK)
   // Only fold this if the inner shift has no other uses -- if it does, folding
diff --git a/test/CodeGen/X86/dagcombine-shifts.ll b/test/CodeGen/X86/dagcombine-shifts.ll
deleted file mode 100644
index 0126edc275..0000000000
--- a/test/CodeGen/X86/dagcombine-shifts.ll
+++ /dev/null
@@ -1,181 +0,0 @@
-; RUN: llc < %s -mtriple=x86_64-linux-gnu | FileCheck %s
-
-; fold (shl (zext (lshr (A, X))), X) -> (zext (shl (lshr (A, X)), X))
-
-; Canolicalize the sequence shl/zext/lshr performing the zeroextend
-; as the last instruction of the sequence.
-; This will help DAGCombiner to identify and then fold the sequence
-; of shifts into a single AND.
-; This transformation is profitable if the shift amounts are the same
-; and if there is only one use of the zext.
-
-define i16 @fun1(i8 zeroext %v) {
-entry:
-  %shr = lshr i8 %v, 4
-  %ext = zext i8 %shr to i16
-  %shl = shl i16 %ext, 4
-  ret i16 %shl
-}
-
-; CHECK-LABEL: @fun1
-; CHECK: and
-; CHECK-NOT: shr
-; CHECK-NOT: shl
-; CHECK: ret
-
-define i32 @fun2(i8 zeroext %v) {
-entry:
-  %shr = lshr i8 %v, 4
-  %ext = zext i8 %shr to i32
-  %shl = shl i32 %ext, 4
-  ret i32 %shl
-}
-
-; CHECK-LABEL: @fun2
-; CHECK: and
-; CHECK-NOT: shr
-; CHECK-NOT: shl
-; CHECK: ret
-
-define i32 @fun3(i16 zeroext %v) {
-entry:
-  %shr = lshr i16 %v, 4
-  %ext = zext i16 %shr to i32
-  %shl = shl i32 %ext, 4
-  ret i32 %shl
-}
-
-; CHECK-LABEL: @fun3
-; CHECK: and
-; CHECK-NOT: shr
-; CHECK-NOT: shl
-; CHECK: ret
-
-define i64 @fun4(i8 zeroext %v) {
-entry:
-  %shr = lshr i8 %v, 4
-  %ext = zext i8 %shr to i64
-  %shl = shl i64 %ext, 4
-  ret i64 %shl
-}
-
-; CHECK-LABEL: @fun4
-; CHECK: and
-; CHECK-NOT: shr
-; CHECK-NOT: shl
-; CHECK: ret
-
-define i64 @fun5(i16 zeroext %v) {
-entry:
-  %shr = lshr i16 %v, 4
-  %ext = zext i16 %shr to i64
-  %shl = shl i64 %ext, 4
-  ret i64 %shl
-}
-
-; CHECK-LABEL: @fun5
-; CHECK: and
-; CHECK-NOT: shr
-; CHECK-NOT: shl
-; CHECK: ret
-
-define i64 @fun6(i32 zeroext %v) {
-entry:
-  %shr = lshr i32 %v, 4
-  %ext = zext i32 %shr to i64
-  %shl = shl i64 %ext, 4
-  ret i64 %shl
-}
-
-; CHECK-LABEL: @fun6
-; CHECK: and
-; CHECK-NOT: shr
-; CHECK-NOT: shl
-; CHECK: ret
-
-; Don't fold the pattern if we use arithmetic shifts.
-
-define i64 @fun7(i8 zeroext %v) {
-entry:
-  %shr = ashr i8 %v, 4
-  %ext = zext i8 %shr to i64
-  %shl = shl i64 %ext, 4
-  ret i64 %shl
-}
-
-; CHECK-LABEL: @fun7
-; CHECK: sar
-; CHECK: shl
-; CHECK: ret
-
-define i64 @fun8(i16 zeroext %v) {
-entry:
-  %shr = ashr i16 %v, 4
-  %ext = zext i16 %shr to i64
-  %shl = shl i64 %ext, 4
-  ret i64 %shl
-}
-
-; CHECK-LABEL: @fun8
-; CHECK: sar
-; CHECK: shl
-; CHECK: ret
-
-define i64 @fun9(i32 zeroext %v) {
-entry:
-  %shr = ashr i32 %v, 4
-  %ext = zext i32 %shr to i64
-  %shl = shl i64 %ext, 4
-  ret i64 %shl
-}
-
-; CHECK-LABEL: @fun9
-; CHECK: sar
-; CHECK: shl
-; CHECK: ret
-
-; Don't fold the pattern if there is more than one use of the
-; operand in input to the shift left.
-
-define i64 @fun10(i8 zeroext %v) {
-entry:
-  %shr = lshr i8 %v, 4
-  %ext = zext i8 %shr to i64
-  %shl = shl i64 %ext, 4
-  %add = add i64 %shl, %ext
-  ret i64 %add
-}
-
-; CHECK-LABEL: @fun10
-; CHECK: shr
-; CHECK: shl
-; CHECK: ret
-
-define i64 @fun11(i16 zeroext %v) {
-entry:
-  %shr = lshr i16 %v, 4
-  %ext = zext i16 %shr to i64
-  %shl = shl i64 %ext, 4
-  %add = add i64 %shl, %ext
-  ret i64 %add
-}
-
-; CHECK-LABEL: @fun11
-; CHECK: shr
-; CHECK: shl
-; CHECK: ret
-
-define i64 @fun12(i32 zeroext %v) {
-entry:
-  %shr = lshr i32 %v, 4
-  %ext = zext i32 %shr to i64
-  %shl = shl i64 %ext, 4
-  %add = add i64 %shl, %ext
-  ret i64 %add
-}
-
-; CHECK-LABEL: @fun12
-; CHECK: shr
-; CHECK: shl
-; CHECK: ret
-