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authorBill Schmidt <wschmidt@linux.vnet.ibm.com>2013-01-17 17:45:19 +0000
committerBill Schmidt <wschmidt@linux.vnet.ibm.com>2013-01-17 17:45:19 +0000
commit792b1233384da442e6c75cf580bd1927123a56f3 (patch)
tree4f3862cab16076f49d17741d5d75ed4b82038acf
parent11af9a873f9e1409a422ab31e22729368805afaf (diff)
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This patch fixes the PPC calling convention to handle returns of
_Complex float and _Complex long double, by simply increasing the number of floating point registers available for return values. The test case verifies that the correct registers are loaded. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172733 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r--lib/Target/PowerPC/PPCCallingConv.td4
-rw-r--r--test/CodeGen/PowerPC/complex-return.ll55
2 files changed, 57 insertions, 2 deletions
diff --git a/lib/Target/PowerPC/PPCCallingConv.td b/lib/Target/PowerPC/PPCCallingConv.td
index 3f87e883b1..120e049f05 100644
--- a/lib/Target/PowerPC/PPCCallingConv.td
+++ b/lib/Target/PowerPC/PPCCallingConv.td
@@ -28,8 +28,8 @@ def RetCC_PPC : CallingConv<[
CCIfType<[i32], CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10]>>,
CCIfType<[i64], CCAssignToReg<[X3, X4, X5, X6]>>,
- CCIfType<[f32], CCAssignToReg<[F1]>>,
- CCIfType<[f64], CCAssignToReg<[F1, F2]>>,
+ CCIfType<[f32], CCAssignToReg<[F1, F2]>>,
+ CCIfType<[f64], CCAssignToReg<[F1, F2, F3, F4]>>,
// Vector types are always returned in V2.
CCIfType<[v16i8, v8i16, v4i32, v4f32], CCAssignToReg<[V2]>>
diff --git a/test/CodeGen/PowerPC/complex-return.ll b/test/CodeGen/PowerPC/complex-return.ll
new file mode 100644
index 0000000000..f12152ff0f
--- /dev/null
+++ b/test/CodeGen/PowerPC/complex-return.ll
@@ -0,0 +1,55 @@
+; RUN: llc -mcpu=pwr7 -O0 < %s | FileCheck %s
+
+target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
+target triple = "powerpc64-unknown-linux-gnu"
+
+define { ppc_fp128, ppc_fp128 } @foo() nounwind {
+entry:
+ %retval = alloca { ppc_fp128, ppc_fp128 }, align 16
+ %x = alloca { ppc_fp128, ppc_fp128 }, align 16
+ %real = getelementptr inbounds { ppc_fp128, ppc_fp128 }* %x, i32 0, i32 0
+ %imag = getelementptr inbounds { ppc_fp128, ppc_fp128 }* %x, i32 0, i32 1
+ store ppc_fp128 0xM400C0000000000000000000000000000, ppc_fp128* %real
+ store ppc_fp128 0xMC00547AE147AE1483CA47AE147AE147A, ppc_fp128* %imag
+ %x.realp = getelementptr inbounds { ppc_fp128, ppc_fp128 }* %x, i32 0, i32 0
+ %x.real = load ppc_fp128* %x.realp
+ %x.imagp = getelementptr inbounds { ppc_fp128, ppc_fp128 }* %x, i32 0, i32 1
+ %x.imag = load ppc_fp128* %x.imagp
+ %real1 = getelementptr inbounds { ppc_fp128, ppc_fp128 }* %retval, i32 0, i32 0
+ %imag2 = getelementptr inbounds { ppc_fp128, ppc_fp128 }* %retval, i32 0, i32 1
+ store ppc_fp128 %x.real, ppc_fp128* %real1
+ store ppc_fp128 %x.imag, ppc_fp128* %imag2
+ %0 = load { ppc_fp128, ppc_fp128 }* %retval
+ ret { ppc_fp128, ppc_fp128 } %0
+}
+
+; CHECK: foo:
+; CHECK: lfd 3
+; CHECK: lfd 4
+; CHECK: lfd 2
+; CHECK: lfd 1
+
+define { float, float } @oof() nounwind {
+entry:
+ %retval = alloca { float, float }, align 4
+ %x = alloca { float, float }, align 4
+ %real = getelementptr inbounds { float, float }* %x, i32 0, i32 0
+ %imag = getelementptr inbounds { float, float }* %x, i32 0, i32 1
+ store float 3.500000e+00, float* %real
+ store float 0xC00547AE20000000, float* %imag
+ %x.realp = getelementptr inbounds { float, float }* %x, i32 0, i32 0
+ %x.real = load float* %x.realp
+ %x.imagp = getelementptr inbounds { float, float }* %x, i32 0, i32 1
+ %x.imag = load float* %x.imagp
+ %real1 = getelementptr inbounds { float, float }* %retval, i32 0, i32 0
+ %imag2 = getelementptr inbounds { float, float }* %retval, i32 0, i32 1
+ store float %x.real, float* %real1
+ store float %x.imag, float* %imag2
+ %0 = load { float, float }* %retval
+ ret { float, float } %0
+}
+
+; CHECK: oof:
+; CHECK: lfs 2
+; CHECK: lfs 1
+