Simplify the tracking of used physregs to a bulk bitor followed by a transitive

closure after allocating all blocks.

Add a few more test cases for -regalloc=fast.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103500 91177308-0d34-0410-b5e6-96231b3b80d8

5 files changed, 29 insertions, 6 deletions

diff --git a/include/llvm/CodeGen/MachineRegisterInfo.h b/include/llvm/CodeGen/MachineRegisterInfo.h
index b377dec378..905be96c35 100644
--- a/include/llvm/CodeGen/MachineRegisterInfo.h
+++ b/include/llvm/CodeGen/MachineRegisterInfo.h
@@ -229,11 +229,18 @@ public:
   /// setPhysRegUsed - Mark the specified register used in this function.
   /// This should only be called during and after register allocation.
   void setPhysRegUsed(unsigned Reg) { UsedPhysRegs[Reg] = true; }
-  
+
+  /// addPhysRegsUsed - Mark the specified registers used in this function.
+  /// This should only be called during and after register allocation.
+  void addPhysRegsUsed(const BitVector &Regs) { UsedPhysRegs |= Regs; }
+
   /// setPhysRegUnused - Mark the specified register unused in this function.
   /// This should only be called during and after register allocation.
   void setPhysRegUnused(unsigned Reg) { UsedPhysRegs[Reg] = false; }
-  
+
+  /// closePhysRegsUsed - Expand UsedPhysRegs to its transitive closure over
+  /// subregisters. That means that if R is used, so are all subregisters.
+  void closePhysRegsUsed(const TargetRegisterInfo&);
 
   //===--------------------------------------------------------------------===//
   // LiveIn/LiveOut Management
diff --git a/lib/CodeGen/MachineRegisterInfo.cpp b/lib/CodeGen/MachineRegisterInfo.cpp
index ef794d5ae3..4a150435ce 100644
--- a/lib/CodeGen/MachineRegisterInfo.cpp
+++ b/lib/CodeGen/MachineRegisterInfo.cpp
@@ -267,6 +267,15 @@ MachineRegisterInfo::EmitLiveInCopies(MachineBasicBlock *EntryMBB,
     EntryMBB->addLiveIn(I->first);
 }
 
+void MachineRegisterInfo::closePhysRegsUsed(const TargetRegisterInfo &TRI) {
+  for (int i = UsedPhysRegs.find_first(); i >= 0;
+       i = UsedPhysRegs.find_next(i))
+         for (const unsigned *SS = TRI.getSubRegisters(i);
+              unsigned SubReg = *SS; ++SS)
+           if (SubReg > i)
+             UsedPhysRegs.set(SubReg);
+}
+
 #ifndef NDEBUG
 void MachineRegisterInfo::dumpUses(unsigned Reg) const {
   for (use_iterator I = use_begin(Reg), E = use_end(); I != E; ++I)
diff --git a/lib/CodeGen/RegAllocFast.cpp b/lib/CodeGen/RegAllocFast.cpp
index 488f630aa6..6bc492ed38 100644
--- a/lib/CodeGen/RegAllocFast.cpp
+++ b/lib/CodeGen/RegAllocFast.cpp
@@ -370,11 +370,9 @@ unsigned RAFast::allocVirtReg(MachineBasicBlock &MBB, MachineInstr *MI,
       if (PhysRegState[BestReg] != regDisabled)
         spillVirtReg(MBB, MI, PhysRegState[BestReg], true);
       else {
-        MF->getRegInfo().setPhysRegUsed(BestReg);
         // Make sure all aliases are disabled.
         for (const unsigned *AS = TRI->getAliasSet(BestReg);
              unsigned Alias = *AS; ++AS) {
-          MF->getRegInfo().setPhysRegUsed(Alias);
           switch (PhysRegState[Alias]) {
           case regDisabled:
             continue;
@@ -443,6 +441,7 @@ unsigned RAFast::reloadVirtReg(MachineBasicBlock &MBB, MachineInstr *MI,
 /// defineVirtReg except the physreg is reverved instead of allocated.
 void RAFast::reservePhysReg(MachineBasicBlock &MBB, MachineInstr *MI,
                             unsigned PhysReg) {
+  UsedInInstr.set(PhysReg);
   switch (unsigned VirtReg = PhysRegState[PhysReg]) {
   case regDisabled:
     break;
@@ -460,6 +459,7 @@ void RAFast::reservePhysReg(MachineBasicBlock &MBB, MachineInstr *MI,
   // This is a disabled register, disable all aliases.
   for (const unsigned *AS = TRI->getAliasSet(PhysReg);
        unsigned Alias = *AS; ++AS) {
+    UsedInInstr.set(Alias);
     switch (unsigned VirtReg = PhysRegState[Alias]) {
     case regDisabled:
     case regFree:
@@ -474,10 +474,8 @@ void RAFast::reservePhysReg(MachineBasicBlock &MBB, MachineInstr *MI,
       break;
     }
     PhysRegState[Alias] = regDisabled;
-    MF->getRegInfo().setPhysRegUsed(Alias);
   }
   PhysRegState[PhysReg] = regReserved;
-  MF->getRegInfo().setPhysRegUsed(PhysReg);
 }
 
 // setPhysReg - Change MO the refer the PhysReg, considering subregs.
@@ -611,6 +609,8 @@ void RAFast::AllocateBasicBlock(MachineBasicBlock &MBB) {
       killPhysReg(PhysKills[i]);
     PhysKills.clear();
 
+    MF->getRegInfo().addPhysRegsUsed(UsedInInstr);
+
     // Track registers defined by instruction - early clobbers at this point.
     UsedInInstr.reset();
     for (unsigned i = 0, e = PhysDefs.size(); i != e; ++i) {
@@ -658,6 +658,8 @@ void RAFast::AllocateBasicBlock(MachineBasicBlock &MBB) {
     for (unsigned i = 0, e = PhysKills.size(); i != e; ++i)
       killPhysReg(PhysKills[i]);
     PhysKills.clear();
+
+    MF->getRegInfo().addPhysRegsUsed(UsedInInstr);
   }
 
   // Spill all physical registers holding virtual registers now.
@@ -693,6 +695,9 @@ bool RAFast::runOnMachineFunction(MachineFunction &Fn) {
        MBB != MBBe; ++MBB)
     AllocateBasicBlock(*MBB);
 
+  // Make sure the set of used physregs is closed under subreg operations.
+  MF->getRegInfo().closePhysRegsUsed(*TRI);
+
   StackSlotForVirtReg.clear();
   return true;
 }
diff --git a/test/CodeGen/X86/fp-stack-O0-crash.ll b/test/CodeGen/X86/fp-stack-O0-crash.ll
index 4768ea2019..bbadca5b86 100644
--- a/test/CodeGen/X86/fp-stack-O0-crash.ll
+++ b/test/CodeGen/X86/fp-stack-O0-crash.ll
@@ -1,4 +1,5 @@
 ; RUN: llc %s -O0 -fast-isel -regalloc=local -o -
+; RUN: llc %s -O0 -fast-isel -regalloc=fast -o -
 ; PR4767
 
 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
diff --git a/test/CodeGen/X86/liveness-local-regalloc.ll b/test/CodeGen/X86/liveness-local-regalloc.ll
index 17e65d8f81..8cac3f8303 100644
--- a/test/CodeGen/X86/liveness-local-regalloc.ll
+++ b/test/CodeGen/X86/liveness-local-regalloc.ll
@@ -1,4 +1,5 @@
 ; RUN: llc < %s -O3 -regalloc=local -mtriple=x86_64-apple-darwin10
+; RUN: llc < %s -O3 -regalloc=fast -mtriple=x86_64-apple-darwin10
 ; <rdar://problem/7755473>
 
 %0 = type { i32, i8*, i8*, %1*, i8*, i64, i64, i32, i32, i32, i32, [1024 x i8] }