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| author | Peter Collingbourne <peter@pcc.me.uk> | 2010-11-13 19:54:30 +0000 |
|---|---|---|
| committer | Peter Collingbourne <peter@pcc.me.uk> | 2010-11-13 19:54:30 +0000 |
| commit | 948cf0289f8280f7e069603837d56c862515c6e1 (patch) | |
| tree | f3490681cdb6b9ee3c28db0f7ab0b9cd74a48346 | |
| parent | 983611836cd1edec8d1b8032e0539b6ed80461d6 (diff) | |
| download | llvm-948cf0289f8280f7e069603837d56c862515c6e1.tar.gz llvm-948cf0289f8280f7e069603837d56c862515c6e1.tar.bz2 llvm-948cf0289f8280f7e069603837d56c862515c6e1.tar.xz | |
Recognise 32-bit ror-based bswap implementation used by uclibc
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119007 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/X86/X86ISelLowering.cpp | 29 | ||||
| -rw-r--r-- | test/CodeGen/X86/bswap-inline-asm.ll | 7 |
2 files changed, 36 insertions, 0 deletions
diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index c82254ca9f..1c5c5108ae 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -11451,6 +11451,35 @@ bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const { } break; case 3: + if (CI->getType()->isIntegerTy(32) && + IA->getConstraintString().compare(0, 5, "=r,0,") == 0) { + SmallVector<StringRef, 4> Words; + SplitString(AsmPieces[0], Words, " \t,"); + if (Words.size() == 3 && Words[0] == "rorw" && Words[1] == "$$8" && + Words[2] == "${0:w}") { + Words.clear(); + SplitString(AsmPieces[1], Words, " \t,"); + if (Words.size() == 3 && Words[0] == "rorl" && Words[1] == "$$16" && + Words[2] == "$0") { + Words.clear(); + SplitString(AsmPieces[2], Words, " \t,"); + if (Words.size() == 3 && Words[0] == "rorw" && Words[1] == "$$8" && + Words[2] == "${0:w}") { + AsmPieces.clear(); + const std::string &Constraints = IA->getConstraintString(); + SplitString(StringRef(Constraints).substr(5), AsmPieces, ","); + std::sort(AsmPieces.begin(), AsmPieces.end()); + if (AsmPieces.size() == 4 && + AsmPieces[0] == "~{cc}" && + AsmPieces[1] == "~{dirflag}" && + AsmPieces[2] == "~{flags}" && + AsmPieces[3] == "~{fpsr}") { + return LowerToBSwap(CI); + } + } + } + } + } if (CI->getType()->isIntegerTy(64) && Constraints.size() >= 2 && Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" && diff --git a/test/CodeGen/X86/bswap-inline-asm.ll b/test/CodeGen/X86/bswap-inline-asm.ll index 2b7019371a..ecb4cecf10 100644 --- a/test/CodeGen/X86/bswap-inline-asm.ll +++ b/test/CodeGen/X86/bswap-inline-asm.ll @@ -65,6 +65,13 @@ define i32 @t32(i32 %x) nounwind { ret i32 %asmtmp } +; CHECK: u32: +; CHECK: bswapl +define i32 @u32(i32 %x) nounwind { + %asmtmp = tail call i32 asm "rorw $$8, ${0:w};rorl $$16, $0;rorw $$8, ${0:w}", "=r,0,~{cc},~{dirflag},~{flags},~{fpsr}"(i32 %x) nounwind + ret i32 %asmtmp +} + ; CHECK: s64: ; CHECK: bswapq define i64 @s64(i64 %x) nounwind { |