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| author | Bruno Cardoso Lopes <bruno.cardoso@gmail.com> | 2011-08-09 17:39:01 +0000 |
|---|---|---|
| committer | Bruno Cardoso Lopes <bruno.cardoso@gmail.com> | 2011-08-09 17:39:01 +0000 |
| commit | a511b8e519b5a13c7ace04a0e77df1e2071f2313 (patch) | |
| tree | c541b729e1481644f5864a170f7c0e35da6601d1 | |
| parent | 4bdd4ed5647f2f9a7b0ccdf6aba920b08ef7b153 (diff) | |
| download | llvm-a511b8e519b5a13c7ace04a0e77df1e2071f2313.tar.gz llvm-a511b8e519b5a13c7ace04a0e77df1e2071f2313.tar.bz2 llvm-a511b8e519b5a13c7ace04a0e77df1e2071f2313.tar.xz | |
Revert r137114
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137127 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/X86/X86ISelLowering.cpp | 22 | ||||
| -rw-r--r-- | test/CodeGen/X86/avx-cvt.ll | 7 |
2 files changed, 1 insertions, 28 deletions
diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index b8197edb2b..71b23e2ccb 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -969,9 +969,6 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM) setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal); setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal); - // sint_to_fp between different vector types needs custom handling - setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Custom); - setOperationAction(ISD::CONCAT_VECTORS, MVT::v4f64, Custom); setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i64, Custom); setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f32, Custom); @@ -7081,24 +7078,6 @@ SDValue X86TargetLowering::LowerShiftParts(SDValue Op, SelectionDAG &DAG) const SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const { EVT SrcVT = Op.getOperand(0).getValueType(); - EVT DstVT = Op.getValueType(); - DebugLoc dl = Op.getDebugLoc(); - - if (SrcVT.isVector() && DstVT.isVector()) { - unsigned SrcVTSize = SrcVT.getSizeInBits(); - unsigned DstVTSize = DstVT.getSizeInBits(); - - // Support directly by the target - if (SrcVTSize == DstVTSize) - return Op; - - // Handle v4f64 = sitofp v4i32 - if (DstVT != MVT::v4f64 && SrcVT != MVT::v4i32) - return SDValue(); - - SDValue V = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, Op.getOperand(0)); - return DAG.getNode(ISD::FP_EXTEND, dl, DstVT, V); - } if (SrcVT.isVector()) return SDValue(); @@ -7115,6 +7094,7 @@ SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op, return Op; } + DebugLoc dl = Op.getDebugLoc(); unsigned Size = SrcVT.getSizeInBits()/8; MachineFunction &MF = DAG.getMachineFunction(); int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false); diff --git a/test/CodeGen/X86/avx-cvt.ll b/test/CodeGen/X86/avx-cvt.ll index 5fe207e060..e45010c903 100644 --- a/test/CodeGen/X86/avx-cvt.ll +++ b/test/CodeGen/X86/avx-cvt.ll @@ -6,13 +6,6 @@ define <8 x float> @sitofp00(<8 x i32> %a) nounwind { ret <8 x float> %b } -; CHECK: vcvtdq2ps -; CHECK-NEXT: vcvtps2pd -define <4 x double> @sitofp01(<4 x i32> %a) { - %b = sitofp <4 x i32> %a to <4 x double> - ret <4 x double> %b -} - ; CHECK: vcvttps2dq %ymm define <8 x i32> @fptosi00(<8 x float> %a) nounwind { %b = fptosi <8 x float> %a to <8 x i32> |