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authorTom Stellard <thomas.stellard@amd.com>2014-04-08 14:27:55 +0000
committerTom Stellard <thomas.stellard@amd.com>2014-04-08 14:27:55 +0000
commitaa3637aafbbe22081f47309184666593cb45b606 (patch)
tree6df1481bae4a4626a828e30f211888d8d9582f3b
parentc428c29241707bf75f94d7c4eabebd1dc1b4a1fd (diff)
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Merging r197572:
------------------------------------------------------------------------ r197572 | rafael.espindola | 2013-12-18 09:35:37 -0500 (Wed, 18 Dec 2013) | 6 lines One ppc32-darwin, a i64 inside a structure can have 32 bit alignment. Thanks for Iain Sandoe for testing this with the original gcc. Clang was already getting this right. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@205766 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r--lib/Target/PowerPC/PPCTargetMachine.cpp3
-rw-r--r--test/CodeGen/PowerPC/anon_aggr.ll4
2 files changed, 4 insertions, 3 deletions
diff --git a/lib/Target/PowerPC/PPCTargetMachine.cpp b/lib/Target/PowerPC/PPCTargetMachine.cpp
index 1d228b613b..44abfbcf6a 100644
--- a/lib/Target/PowerPC/PPCTargetMachine.cpp
+++ b/lib/Target/PowerPC/PPCTargetMachine.cpp
@@ -48,7 +48,8 @@ static std::string getDataLayoutString(const PPCSubtarget &ST) {
// Note, the alignment values for f64 and i64 on ppc64 in Darwin
// documentation are wrong; these are correct (i.e. "what gcc does").
- Ret += "-f64:64:64-i64:64:64";
+ if (ST.isPPC64() || ST.isSVR4ABI())
+ Ret += "-f64:64:64-i64:64:64";
// Set support for 128 floats depending on the ABI.
if (ST.isPPC64() && ST.isSVR4ABI()) {
diff --git a/test/CodeGen/PowerPC/anon_aggr.ll b/test/CodeGen/PowerPC/anon_aggr.ll
index 1525e05501..ce07d8845d 100644
--- a/test/CodeGen/PowerPC/anon_aggr.ll
+++ b/test/CodeGen/PowerPC/anon_aggr.ll
@@ -119,9 +119,9 @@ unequal:
; CHECK: ld 3, -[[OFFSET1]](1)
; DARWIN32: _func3:
-; DARWIN32: addi r[[REG1:[0-9]+]], r[[REGSP:[0-9]+]], 40
+; DARWIN32: addi r[[REG1:[0-9]+]], r[[REGSP:[0-9]+]], 36
; DARWIN32: addi r[[REG2:[0-9]+]], r[[REGSP]], 24
-; DARWIN32: lwz r[[REG3:[0-9]+]], 48(r[[REGSP]])
+; DARWIN32: lwz r[[REG3:[0-9]+]], 44(r[[REGSP]])
; DARWIN32: lwz r[[REG4:[0-9]+]], 32(r[[REGSP]])
; DARWIN32: cmplw cr{{[0-9]+}}, r[[REG4]], r[[REG3]]
; DARWIN32: stw r[[REG3]], -[[OFFSET1:[0-9]+]]