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author | Anton Korobeynikov <asl@math.spbu.ru> | 2012-11-16 21:15:20 +0000 |
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committer | Anton Korobeynikov <asl@math.spbu.ru> | 2012-11-16 21:15:20 +0000 |
commit | b1a392e7c50da5789cf5da879c5b81b72c751c21 (patch) | |
tree | 222681be0c5cd56ecb12c7fd738efc1008b3d7d1 | |
parent | ccc015d4314e966253668deec2b18a0d3e0cf4c0 (diff) | |
download | llvm-b1a392e7c50da5789cf5da879c5b81b72c751c21.tar.gz llvm-b1a392e7c50da5789cf5da879c5b81b72c751c21.tar.bz2 llvm-b1a392e7c50da5789cf5da879c5b81b72c751c21.tar.xz |
Make sure FABS on v2f32 and v4f32 is legal on ARM NEON
This fixes PR14359
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168200 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r-- | lib/Target/ARM/ARMISelLowering.cpp | 1 | ||||
-rw-r--r-- | lib/Target/ARM/ARMInstrNEON.td | 15 | ||||
-rw-r--r-- | test/CodeGen/ARM/fabs-neon.ll | 17 |
3 files changed, 26 insertions, 7 deletions
diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp index f53d664268..3dd08d93bf 100644 --- a/lib/Target/ARM/ARMISelLowering.cpp +++ b/lib/Target/ARM/ARMISelLowering.cpp @@ -505,7 +505,6 @@ ARMTargetLowering::ARMTargetLowering(TargetMachine &TM) setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Expand); setOperationAction(ISD::FFLOOR, MVT::v2f64, Expand); - setOperationAction(ISD::FABS, MVT::v4f32, Expand); setOperationAction(ISD::FSQRT, MVT::v4f32, Expand); setOperationAction(ISD::FSIN, MVT::v4f32, Expand); setOperationAction(ISD::FCOS, MVT::v4f32, Expand); diff --git a/lib/Target/ARM/ARMInstrNEON.td b/lib/Target/ARM/ARMInstrNEON.td index 3cf213cbff..697a8d28c5 100644 --- a/lib/Target/ARM/ARMInstrNEON.td +++ b/lib/Target/ARM/ARMInstrNEON.td @@ -4877,12 +4877,15 @@ defm VSRI : N2VShInsR_QHSD<1, 1, 0b0100, 1, "vsri">; defm VABS : N2VInt_QHS<0b11, 0b11, 0b01, 0b00110, 0, IIC_VUNAiD, IIC_VUNAiQ, "vabs", "s", int_arm_neon_vabs>; -def VABSfd : N2VDInt<0b11, 0b11, 0b10, 0b01, 0b01110, 0, - IIC_VUNAD, "vabs", "f32", - v2f32, v2f32, int_arm_neon_vabs>; -def VABSfq : N2VQInt<0b11, 0b11, 0b10, 0b01, 0b01110, 0, - IIC_VUNAQ, "vabs", "f32", - v4f32, v4f32, int_arm_neon_vabs>; +def VABSfd : N2VD<0b11, 0b11, 0b10, 0b01, 0b01110, 0, + "vabs", "f32", + v2f32, v2f32, fabs>; +def VABSfq : N2VQ<0b11, 0b11, 0b10, 0b01, 0b01110, 0, + "vabs", "f32", + v4f32, v4f32, fabs>; + +def : Pat<(v2f32 (int_arm_neon_vabs (v2f32 DPR:$src))), (VABSfd DPR:$src)>; +def : Pat<(v4f32 (int_arm_neon_vabs (v4f32 QPR:$src))), (VABSfq QPR:$src)>; // VQABS : Vector Saturating Absolute Value defm VQABS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01110, 0, diff --git a/test/CodeGen/ARM/fabs-neon.ll b/test/CodeGen/ARM/fabs-neon.ll new file mode 100644 index 0000000000..614117ff7b --- /dev/null +++ b/test/CodeGen/ARM/fabs-neon.ll @@ -0,0 +1,17 @@ +; RUN: llc < %s -mtriple=armv7-eabi -float-abi=hard -mcpu=cortex-a8 | FileCheck %s + +; CHECK: test: +; CHECK: vabs.f32 q0, q0 +define <4 x float> @test(<4 x float> %a) { + %foo = call <4 x float> @llvm.fabs.v4f32(<4 x float> %a) + ret <4 x float> %foo +} +declare <4 x float> @llvm.fabs.v4f32(<4 x float> %a) + +; CHECK: test2: +; CHECK: vabs.f32 d0, d0 +define <2 x float> @test2(<2 x float> %a) { + %foo = call <2 x float> @llvm.fabs.v2f32(<2 x float> %a) + ret <2 x float> %foo +} +declare <2 x float> @llvm.fabs.v2f32(<2 x float> %a) |