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| author | Tom Stellard <thomas.stellard@amd.com> | 2014-03-24 18:21:29 +0000 |
|---|---|---|
| committer | Tom Stellard <thomas.stellard@amd.com> | 2014-03-24 18:21:29 +0000 |
| commit | bcc1d80afbd2403ad02fa5ba9b3ae0779c24413b (patch) | |
| tree | e79370476c202e52ca39bdd1e370b6df4aad3906 | |
| parent | 6392836b79fc7d525323b5680f1a90d8b6e47c6d (diff) | |
| download | llvm-bcc1d80afbd2403ad02fa5ba9b3ae0779c24413b.tar.gz llvm-bcc1d80afbd2403ad02fa5ba9b3ae0779c24413b.tar.bz2 llvm-bcc1d80afbd2403ad02fa5ba9b3ae0779c24413b.tar.xz | |
Merging r199918:
------------------------------------------------------------------------
r199918 | thomas.stellard | 2014-01-23 10:49:33 -0800 (Thu, 23 Jan 2014) | 8 lines
R600: Disable the BFE pattern
This pattern uses an SDNodeXForm, which isn't being emitted for some
reason. I can get it to work by attaching the PatLeaf that has the
XForm to the argument in the output pattern, but this results in an
immediate being used in a register operand, which the backend can't
handle yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@204640 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/R600/AMDGPUInstructions.td | 7 | ||||
| -rw-r--r-- | lib/Target/R600/R600Instructions.td | 4 | ||||
| -rw-r--r-- | test/CodeGen/R600/bfe_uint.ll | 2 |
3 files changed, 12 insertions, 1 deletions
diff --git a/lib/Target/R600/AMDGPUInstructions.td b/lib/Target/R600/AMDGPUInstructions.td index 3c5375d84e..7acd67313e 100644 --- a/lib/Target/R600/AMDGPUInstructions.td +++ b/lib/Target/R600/AMDGPUInstructions.td @@ -388,6 +388,11 @@ class SHA256MaPattern <Instruction BFI_INT, Instruction XOR> : Pat < // Bitfield extract patterns +/* + +XXX: The BFE pattern is not working correctly because the XForm is not being +applied. + def legalshift32 : ImmLeaf <i32, [{return Imm >=0 && Imm < 32;}]>; def bfemask : PatLeaf <(imm), [{return isMask_32(N->getZExtValue());}], SDNodeXForm<imm, [{ return CurDAG->getTargetConstant(CountTrailingOnes_32(N->getZExtValue()), MVT::i32);}]>>; @@ -397,6 +402,8 @@ class BFEPattern <Instruction BFE> : Pat < (BFE $x, $y, $z) >; +*/ + // rotr pattern class ROTRPattern <Instruction BIT_ALIGN> : Pat < (rotr i32:$src0, i32:$src1), diff --git a/lib/Target/R600/R600Instructions.td b/lib/Target/R600/R600Instructions.td index 0346e24ab7..5e0e3349ad 100644 --- a/lib/Target/R600/R600Instructions.td +++ b/lib/Target/R600/R600Instructions.td @@ -1516,7 +1516,9 @@ let Predicates = [isEGorCayman] in { i32:$src2))], VecALU >; - def : BFEPattern <BFE_UINT_eg>; +// XXX: This pattern is broken, disabling for now. See comment in +// AMDGPUInstructions.td for more info. +// def : BFEPattern <BFE_UINT_eg>; def BFI_INT_eg : R600_3OP <0x06, "BFI_INT", [], VecALU>; defm : BFIPatterns <BFI_INT_eg>; diff --git a/test/CodeGen/R600/bfe_uint.ll b/test/CodeGen/R600/bfe_uint.ll index 92570c3152..fe466e6ad5 100644 --- a/test/CodeGen/R600/bfe_uint.ll +++ b/test/CodeGen/R600/bfe_uint.ll @@ -1,5 +1,7 @@ ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s +; XFAIL: * + ; CHECK: @bfe_def ; CHECK: BFE_UINT define void @bfe_def(i32 addrspace(1)* %out, i32 %x) { |