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| author | Bill Wendling <isanbard@gmail.com> | 2009-04-29 00:15:41 +0000 |
|---|---|---|
| committer | Bill Wendling <isanbard@gmail.com> | 2009-04-29 00:15:41 +0000 |
| commit | be8cc2a3dedeb7685f07e68cdc4b9502eb97eb2b (patch) | |
| tree | 61b5516b5232ee39d0cfb04473b2cc8076464a1c | |
| parent | a24d1b155831d25f543e0e4ece9b572cefda2f17 (diff) | |
| download | llvm-be8cc2a3dedeb7685f07e68cdc4b9502eb97eb2b.tar.gz llvm-be8cc2a3dedeb7685f07e68cdc4b9502eb97eb2b.tar.bz2 llvm-be8cc2a3dedeb7685f07e68cdc4b9502eb97eb2b.tar.xz | |
Second attempt:
Massive check in. This changes the "-fast" flag to "-O#" in llc. If you want to
use the old behavior, the flag is -O0. This change allows for finer-grained
control over which optimizations are run at different -O levels.
Most of this work was pretty mechanical. The majority of the fixes came from
verifying that a "fast" variable wasn't used anymore. The JIT still uses a
"Fast" flag. I'll change the JIT with a follow-up patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70343 91177308-0d34-0410-b5e6-96231b3b80d8
93 files changed, 400 insertions, 346 deletions
diff --git a/docs/CommandGuide/llc.pod b/docs/CommandGuide/llc.pod index f5fd34f01a..eba7859e28 100644 --- a/docs/CommandGuide/llc.pod +++ b/docs/CommandGuide/llc.pod @@ -41,6 +41,12 @@ Other B<llc> options are as follows: Print a summary of command line options. +=item B<-O>=I<uint> + +Generate code at different optimization levels. These correspond to the I<-O0>, +I<-O1>, I<-O2>, I<-O3>, and I<-O4> optimization levels used by B<llvm-gcc> and +B<clang>. + =item B<-f> Overwrite output files. By default, B<llc> will refuse to overwrite diff --git a/include/llvm/CodeGen/AsmPrinter.h b/include/llvm/CodeGen/AsmPrinter.h index d4e0c43219..3f61d74e13 100644 --- a/include/llvm/CodeGen/AsmPrinter.h +++ b/include/llvm/CodeGen/AsmPrinter.h @@ -65,8 +65,8 @@ namespace llvm { // Necessary for external weak linkage support std::set<const GlobalValue*> ExtWeakSymbols; - /// Fast - Generating code via fast instruction selection. - bool Fast; + /// OptLevel - Generating code at a specific optimization level. + unsigned OptLevel; public: /// Output stream on which we're printing assembly code. /// @@ -110,8 +110,8 @@ namespace llvm { bool VerboseAsm; protected: - AsmPrinter(raw_ostream &o, TargetMachine &TM, - const TargetAsmInfo *T, bool F, bool V); + explicit AsmPrinter(raw_ostream &o, TargetMachine &TM, + const TargetAsmInfo *T, unsigned OL, bool V); public: virtual ~AsmPrinter(); diff --git a/include/llvm/CodeGen/DwarfWriter.h b/include/llvm/CodeGen/DwarfWriter.h index 4b35b288c9..5641407001 100644 --- a/include/llvm/CodeGen/DwarfWriter.h +++ b/include/llvm/CodeGen/DwarfWriter.h @@ -81,7 +81,7 @@ public: void EndFunction(MachineFunction *MF); /// ValidDebugInfo - Return true if V represents valid debug info value. - bool ValidDebugInfo(Value *V, bool FastISel); + bool ValidDebugInfo(Value *V, unsigned OptLevel); /// RecordSourceLine - Register a source line with debug info. Returns a /// unique label ID used to generate a label and provide correspondence to diff --git a/include/llvm/CodeGen/LinkAllCodegenComponents.h b/include/llvm/CodeGen/LinkAllCodegenComponents.h index 74026a4791..84d9819c2d 100644 --- a/include/llvm/CodeGen/LinkAllCodegenComponents.h +++ b/include/llvm/CodeGen/LinkAllCodegenComponents.h @@ -42,11 +42,11 @@ namespace { llvm::linkOcamlGC(); llvm::linkShadowStackGC(); - (void) llvm::createBURRListDAGScheduler(NULL, false); - (void) llvm::createTDRRListDAGScheduler(NULL, false); - (void) llvm::createTDListDAGScheduler(NULL, false); - (void) llvm::createFastDAGScheduler(NULL, false); - (void) llvm::createDefaultScheduler(NULL, false); + (void) llvm::createBURRListDAGScheduler(NULL, 3); + (void) llvm::createTDRRListDAGScheduler(NULL, 3); + (void) llvm::createTDListDAGScheduler(NULL, 3); + (void) llvm::createFastDAGScheduler(NULL, 3); + (void) llvm::createDefaultScheduler(NULL, 3); } } ForceCodegenLinking; // Force link by creating a global definition. diff --git a/include/llvm/CodeGen/SchedulerRegistry.h b/include/llvm/CodeGen/SchedulerRegistry.h index c967bfc446..e02dc7a392 100644 --- a/include/llvm/CodeGen/SchedulerRegistry.h +++ b/include/llvm/CodeGen/SchedulerRegistry.h @@ -32,7 +32,7 @@ class MachineBasicBlock; class RegisterScheduler : public MachinePassRegistryNode { public: - typedef ScheduleDAGSDNodes *(*FunctionPassCtor)(SelectionDAGISel*, bool); + typedef ScheduleDAGSDNodes *(*FunctionPassCtor)(SelectionDAGISel*, unsigned); static MachinePassRegistry Registry; @@ -64,27 +64,27 @@ public: /// createBURRListDAGScheduler - This creates a bottom up register usage /// reduction list scheduler. ScheduleDAGSDNodes *createBURRListDAGScheduler(SelectionDAGISel *IS, - bool Fast); + unsigned OptLevel); /// createTDRRListDAGScheduler - This creates a top down register usage /// reduction list scheduler. ScheduleDAGSDNodes *createTDRRListDAGScheduler(SelectionDAGISel *IS, - bool Fast); + unsigned OptLevel); /// createTDListDAGScheduler - This creates a top-down list scheduler with /// a hazard recognizer. ScheduleDAGSDNodes *createTDListDAGScheduler(SelectionDAGISel *IS, - bool Fast); + unsigned OptLevel); /// createFastDAGScheduler - This creates a "fast" scheduler. /// ScheduleDAGSDNodes *createFastDAGScheduler(SelectionDAGISel *IS, - bool Fast); + unsigned OptLevel); /// createDefaultScheduler - This creates an instruction scheduler appropriate /// for the target. ScheduleDAGSDNodes *createDefaultScheduler(SelectionDAGISel *IS, - bool Fast); + unsigned OptLevel); } // end namespace llvm diff --git a/include/llvm/CodeGen/SelectionDAG.h b/include/llvm/CodeGen/SelectionDAG.h index a350d5fd93..d2d17cfa2e 100644 --- a/include/llvm/CodeGen/SelectionDAG.h +++ b/include/llvm/CodeGen/SelectionDAG.h @@ -202,7 +202,7 @@ public: /// certain types of nodes together, or eliminating superfluous nodes. The /// Level argument controls whether Combine is allowed to produce nodes and /// types that are illegal on the target. - void Combine(CombineLevel Level, AliasAnalysis &AA, bool Fast); + void Combine(CombineLevel Level, AliasAnalysis &AA, unsigned OptLevel); /// LegalizeTypes - This transforms the SelectionDAG into a SelectionDAG that /// only uses types natively supported by the target. Returns "true" if it @@ -218,7 +218,7 @@ public: /// /// Note that this is an involved process that may invalidate pointers into /// the graph. - void Legalize(bool TypesNeedLegalizing, bool Fast); + void Legalize(bool TypesNeedLegalizing, unsigned OptLevel); /// RemoveDeadNodes - This method deletes all unreachable nodes in the /// SelectionDAG. diff --git a/include/llvm/CodeGen/SelectionDAGISel.h b/include/llvm/CodeGen/SelectionDAGISel.h index e6bf8d76f4..d8802c7d9d 100644 --- a/include/llvm/CodeGen/SelectionDAGISel.h +++ b/include/llvm/CodeGen/SelectionDAGISel.h @@ -51,10 +51,10 @@ public: MachineBasicBlock *BB; AliasAnalysis *AA; GCFunctionInfo *GFI; - bool Fast; + unsigned OptLevel; static char ID; - explicit SelectionDAGISel(TargetMachine &tm, bool fast = false); + explicit SelectionDAGISel(TargetMachine &tm, unsigned OL = 3); virtual ~SelectionDAGISel(); TargetLowering &getTargetLowering() { return TLI; } diff --git a/include/llvm/Target/TargetMachine.h b/include/llvm/Target/TargetMachine.h index c4c0b0ec24..ba688b48de 100644 --- a/include/llvm/Target/TargetMachine.h +++ b/include/llvm/Target/TargetMachine.h @@ -213,7 +213,7 @@ public: virtual FileModel::Model addPassesToEmitFile(PassManagerBase &, raw_ostream &, CodeGenFileType, - bool /*Fast*/) { + unsigned /* OptLevel */) { return FileModel::None; } @@ -222,7 +222,8 @@ public: /// used to finish up adding passes to emit the file, if necessary. /// virtual bool addPassesToEmitFileFinish(PassManagerBase &, - MachineCodeEmitter *, bool /*Fast*/) { + MachineCodeEmitter *, + unsigned /* OptLevel */) { return true; } @@ -234,7 +235,7 @@ public: /// virtual bool addPassesToEmitMachineCode(PassManagerBase &, MachineCodeEmitter &, - bool /*Fast*/) { + unsigned /* OptLevel */) { return true; } @@ -243,7 +244,8 @@ public: /// use this. virtual bool WantsWholeFile() const { return false; } virtual bool addPassesToEmitWholeFile(PassManager &, raw_ostream &, - CodeGenFileType, bool /*Fast*/) { + CodeGenFileType, + unsigned /* OptLevel */) { return true; } }; @@ -258,16 +260,16 @@ protected: // Can only create subclasses. /// addCommonCodeGenPasses - Add standard LLVM codegen passes used for /// both emitting to assembly files or machine code output. /// - bool addCommonCodeGenPasses(PassManagerBase &, bool /*Fast*/); + bool addCommonCodeGenPasses(PassManagerBase &, unsigned /* OptLevel */); public: /// addPassesToEmitFile - Add passes to the specified pass manager to get the /// specified file emitted. Typically this will involve several steps of code - /// generation. If Fast is set to true, the code generator should emit code - /// as fast as possible, though the generated code may be less efficient. - /// This method should return FileModel::Error if emission of this file type - /// is not supported. + /// generation. If OptLevel is 0, the code generator should emit code as fast + /// as possible, though the generated code may be less efficient. This method + /// should return FileModel::Error if emission of this file type is not + /// supported. /// /// The default implementation of this method adds components from the /// LLVM retargetable code generator, invoking the methods below to get @@ -276,14 +278,15 @@ public: virtual FileModel::Model addPassesToEmitFile(PassManagerBase &PM, raw_ostream &Out, CodeGenFileType FileType, - bool Fast); + unsigned OptLevel); /// addPassesToEmitFileFinish - If the passes to emit the specified file had /// to be split up (e.g., to add an object writer pass), this method can be /// used to finish up adding passes to emit the file, if necessary. /// virtual bool addPassesToEmitFileFinish(PassManagerBase &PM, - MachineCodeEmitter *MCE, bool Fast); + MachineCodeEmitter *MCE, + unsigned OptLevel); /// addPassesToEmitMachineCode - Add passes to the specified pass manager to /// get machine code emitted. This uses a MachineCodeEmitter object to handle @@ -292,21 +295,22 @@ public: /// not supported. /// virtual bool addPassesToEmitMachineCode(PassManagerBase &PM, - MachineCodeEmitter &MCE, bool Fast); + MachineCodeEmitter &MCE, + unsigned OptLevel); /// Target-Independent Code Generator Pass Configuration Options. /// addInstSelector - This method should add any "last minute" LLVM->LLVM /// passes, then install an instruction selector pass, which converts from /// LLVM code to machine instructions. - virtual bool addInstSelector(PassManagerBase &, bool /*Fast*/) { + virtual bool addInstSelector(PassManagerBase &, unsigned /* OptLevel */) { return true; } /// addPreRegAllocPasses - This method may be implemented by targets that want /// to run passes immediately before register allocation. This should return /// true if -print-machineinstrs should print after these passes. - virtual bool addPreRegAlloc(PassManagerBase &, bool /*Fast*/) { + virtual bool addPreRegAlloc(PassManagerBase &, unsigned /* OptLevel */) { return false; } @@ -314,14 +318,14 @@ public: /// want to run passes after register allocation but before prolog-epilog /// insertion. This should return true if -print-machineinstrs should print /// after these passes. - virtual bool addPostRegAlloc(PassManagerBase &, bool /*Fast*/) { + virtual bool addPostRegAlloc(PassManagerBase &, unsigned /* OptLevel */) { return false; } /// addPreEmitPass - This pass may be implemented by targets that want to run /// passes immediately before machine code is emitted. This should return /// true if -print-machineinstrs should print out the code after the passes. - virtual bool addPreEmitPass(PassManagerBase &, bool /*Fast*/) { + virtual bool addPreEmitPass(PassManagerBase &, unsigned /* OptLevel */) { return false; } @@ -329,7 +333,7 @@ public: /// addAssemblyEmitter - This pass should be overridden by the target to add /// the asmprinter, if asm emission is supported. If this is not supported, /// 'true' should be returned. - virtual bool addAssemblyEmitter(PassManagerBase &, bool /*Fast*/, + virtual bool addAssemblyEmitter(PassManagerBase &, unsigned /* OptLevel */, bool /* VerboseAsmDefault */, raw_ostream &) { return true; } @@ -337,7 +341,7 @@ public: /// addCodeEmitter - This pass should be overridden by the target to add a /// code emitter, if supported. If this is not supported, 'true' should be /// returned. If DumpAsm is true, the generated assembly is printed to cerr. - virtual bool addCodeEmitter(PassManagerBase &, bool /*Fast*/, + virtual bool addCodeEmitter(PassManagerBase &, unsigned /* OptLevel */, bool /*DumpAsm*/, MachineCodeEmitter &) { return true; } @@ -346,7 +350,7 @@ public: /// a code emitter (without setting flags), if supported. If this is not /// supported, 'true' should be returned. If DumpAsm is true, the generated /// assembly is printed to cerr. - virtual bool addSimpleCodeEmitter(PassManagerBase &, bool /*Fast*/, + virtual bool addSimpleCodeEmitter(PassManagerBase &, unsigned /* OptLevel */, bool /*DumpAsm*/, MachineCodeEmitter &) { return true; } diff --git a/lib/CodeGen/AsmPrinter/AsmPrinter.cpp b/lib/CodeGen/AsmPrinter/AsmPrinter.cpp index a815aabe5c..e0a526c372 100644 --- a/lib/CodeGen/AsmPrinter/AsmPrinter.cpp +++ b/lib/CodeGen/AsmPrinter/AsmPrinter.cpp @@ -42,8 +42,8 @@ AsmVerbose("asm-verbose", cl::desc("Add comments to directives."), char AsmPrinter::ID = 0; AsmPrinter::AsmPrinter(raw_ostream &o, TargetMachine &tm, - const TargetAsmInfo *T, bool F, bool VDef) - : MachineFunctionPass(&ID), FunctionNumber(0), Fast(F), O(o), + const TargetAsmInfo *T, unsigned OL, bool VDef) + : MachineFunctionPass(&ID), FunctionNumber(0), OptLevel(OL), O(o), TM(tm), TAI(T), TRI(tm.getRegisterInfo()), IsInTextSection(false) { diff --git a/lib/CodeGen/AsmPrinter/DwarfWriter.cpp b/lib/CodeGen/AsmPrinter/DwarfWriter.cpp index 73326135a6..5d6a70f622 100644 --- a/lib/CodeGen/AsmPrinter/DwarfWriter.cpp +++ b/lib/CodeGen/AsmPrinter/DwarfWriter.cpp @@ -3351,7 +3351,7 @@ public: } /// ValidDebugInfo - Return true if V represents valid debug info value. - bool ValidDebugInfo(Value *V, bool FastISel) { + bool ValidDebugInfo(Value *V, unsigned OptLevel) { if (!V) return false; @@ -3393,7 +3393,7 @@ public: case DW_TAG_lexical_block: /// FIXME. This interfers with the qualitfy of generated code when /// during optimization. - if (FastISel == false) + if (OptLevel != 0) return false; default: break; @@ -3574,7 +3574,7 @@ public: return 0; SmallVector<DbgScope *, 2> &Scopes = I->second; - if (Scopes.empty()) return 0; + assert(!Scopes.empty() && "We should have at least one debug scope!"); DbgScope *Scope = Scopes.back(); Scopes.pop_back(); unsigned ID = MMI->NextLabelID(); MMI->RecordUsedDbgLabel(ID); @@ -4731,8 +4731,8 @@ void DwarfWriter::EndFunction(MachineFunction *MF) { } /// ValidDebugInfo - Return true if V represents valid debug info value. -bool DwarfWriter::ValidDebugInfo(Value *V, bool FastISel) { - return DD && DD->ValidDebugInfo(V, FastISel); +bool DwarfWriter::ValidDebugInfo(Value *V, unsigned OptLevel) { + return DD && DD->ValidDebugInfo(V, OptLevel); } /// RecordSourceLine - Records location information and associates it with a diff --git a/lib/CodeGen/LLVMTargetMachine.cpp b/lib/CodeGen/LLVMTargetMachine.cpp index 086104912b..92aeb64c7d 100644 --- a/lib/CodeGen/LLVMTargetMachine.cpp +++ b/lib/CodeGen/LLVMTargetMachine.cpp @@ -55,9 +55,9 @@ FileModel::Model LLVMTargetMachine::addPassesToEmitFile(PassManagerBase &PM, raw_ostream &Out, CodeGenFileType FileType, - bool Fast) { + unsigned OptLevel) { // Add common CodeGen passes. - if (addCommonCodeGenPasses(PM, Fast)) + if (addCommonCodeGenPasses(PM, OptLevel)) return FileModel::Error; // Fold redundant debug labels. @@ -66,17 +66,17 @@ LLVMTargetMachine::addPassesToEmitFile(PassManagerBase &PM, if (PrintMachineCode) PM.add(createMachineFunctionPrinterPass(cerr)); - if (addPreEmitPass(PM, Fast) && PrintMachineCode) + if (addPreEmitPass(PM, OptLevel) && PrintMachineCode) PM.add(createMachineFunctionPrinterPass(cerr)); - if (!Fast) + if (OptLevel != 0) PM.add(createLoopAlignerPass()); switch (FileType) { default: break; case TargetMachine::AssemblyFile: - if (addAssemblyEmitter(PM, Fast, getAsmVerbosityDefault(), Out)) + if (addAssemblyEmitter(PM, OptLevel, getAsmVerbosityDefault(), Out)) return FileModel::Error; return FileModel::AsmFile; case TargetMachine::ObjectFile: @@ -94,9 +94,9 @@ LLVMTargetMachine::addPassesToEmitFile(PassManagerBase &PM, /// finish up adding passes to emit the file, if necessary. bool LLVMTargetMachine::addPassesToEmitFileFinish(PassManagerBase &PM, MachineCodeEmitter *MCE, - bool Fast) { + unsigned OptLevel) { if (MCE) - addSimpleCodeEmitter(PM, Fast, PrintEmittedAsm, *MCE); + addSimpleCodeEmitter(PM, OptLevel, PrintEmittedAsm, *MCE); PM.add(createGCInfoDeleter()); @@ -114,15 +114,15 @@ bool LLVMTargetMachine::addPassesToEmitFileFinish(PassManagerBase &PM, /// bool LLVMTargetMachine::addPassesToEmitMachineCode(PassManagerBase &PM, MachineCodeEmitter &MCE, - bool Fast) { + unsigned OptLevel) { // Add common CodeGen passes. - if (addCommonCodeGenPasses(PM, Fast)) + if (addCommonCodeGenPasses(PM, OptLevel)) return true; - if (addPreEmitPass(PM, Fast) && PrintMachineCode) + if (addPreEmitPass(PM, OptLevel) && PrintMachineCode) PM.add(createMachineFunctionPrinterPass(cerr)); - addCodeEmitter(PM, Fast, PrintEmittedAsm, MCE); + addCodeEmitter(PM, OptLevel, PrintEmittedAsm, MCE); PM.add(createGCInfoDeleter()); @@ -135,11 +135,12 @@ bool LLVMTargetMachine::addPassesToEmitMachineCode(PassManagerBase &PM, /// addCommonCodeGenPasses - Add standard LLVM codegen passes used for /// both emitting to assembly files or machine code output. /// -bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM, bool Fast) { +bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM, + unsigned OptLevel) { // Standard LLVM-Level Passes. // Run loop strength reduction before anything else. - if (!Fast) { + if (OptLevel != 0) { PM.add(createLoopStrengthReducePass(getTargetLowering())); if (PrintLSR) PM.add(createPrintFunctionPass("\n\n*** Code after LSR ***\n", &errs())); @@ -153,7 +154,7 @@ bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM, bool Fast) { // Make sure that no unreachable blocks are instruction selected. PM.add(createUnreachableBlockEliminationPass()); - if (!Fast) + if (OptLevel != 0) PM.add(createCodeGenPreparePass(getTargetLowering())); PM.add(createStackProtectorPass(getTargetLowering())); @@ -167,38 +168,38 @@ bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM, bool Fast) { // Enable FastISel with -fast, but allow that to be overridden. if (EnableFastISelOption == cl::BOU_TRUE || - (Fast && EnableFastISelOption != cl::BOU_FALSE)) + (OptLevel == 0 && EnableFastISelOption != cl::BOU_FALSE)) EnableFastISel = true; // Ask the target for an isel. - if (addInstSelector(PM, Fast)) + if (addInstSelector(PM, OptLevel)) return true; // Print the instruction selected machine code... if (PrintMachineCode) PM.add(createMachineFunctionPrinterPass(cerr)); - if (!Fast) { + if (OptLevel != 0) { PM.add(createMachineLICMPass()); PM.add(createMachineSinkingPass()); } // Run pre-ra passes. - if (addPreRegAlloc(PM, Fast) && PrintMachineCode) + if (addPreRegAlloc(PM, OptLevel) && PrintMachineCode) PM.add(createMachineFunctionPrinterPass(cerr)); // Perform register allocation. PM.add(createRegisterAllocator()); // Perform stack slot coloring. - if (!Fast) + if (OptLevel != 0) PM.add(createStackSlotColoringPass()); if (PrintMachineCode) // Print the register-allocated code PM.add(createMachineFunctionPrinterPass(cerr)); // Run post-ra passes. - if (addPostRegAlloc(PM, Fast) && PrintMachineCode) + if (addPostRegAlloc(PM, OptLevel) && PrintMachineCode) PM.add(createMachineFunctionPrinterPass(cerr)); if (PrintMachineCode) @@ -216,7 +217,7 @@ bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM, bool Fast) { PM.add(createMachineFunctionPrinterPass(cerr)); // Second pass scheduler. - if (!Fast && !DisablePostRAScheduler) { + if (OptLevel != 0 && !DisablePostRAScheduler) { PM.add(createPostRAScheduler()); if (PrintMachineCode) @@ -224,7 +225,7 @@ bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM, bool Fast) { } // Branch folding must be run after regalloc and prolog/epilog insertion. - if (!Fast) + if (OptLevel != 0) PM.add(createBranchFoldingPass(getEnableTailMergeDefault())); if (PrintMachineCode) diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index bd724afa54..8a41423cbe 100644 --- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -57,9 +57,9 @@ namespace { SelectionDAG &DAG; const TargetLowering &TLI; CombineLevel Level; + unsigned OptLevel; bool LegalOperations; bool LegalTypes; - bool Fast; // Worklist of all of the nodes that need to be simplified. std::vector<SDNode*> WorkList; @@ -254,13 +254,13 @@ namespace { } public: - DAGCombiner(SelectionDAG &D, AliasAnalysis &A, bool fast) + DAGCombiner(SelectionDAG &D, AliasAnalysis &A, unsigned OL) : DAG(D), TLI(D.getTargetLoweringInfo()), Level(Unrestricted), + OptLevel(OL), LegalOperations(false), LegalTypes(false), - Fast(fast), AA(A) {} /// Run - runs the dag combiner on all nodes in the work list @@ -4784,7 +4784,7 @@ SDValue DAGCombiner::visitLOAD(SDNode *N) { SDValue Ptr = LD->getBasePtr(); // Try to infer better alignment information than the load already has. - if (!Fast && LD->isUnindexed()) { + if (OptLevel != 0 && LD->isUnindexed()) { if (unsigned Align = InferAlignment(Ptr, DAG)) { if (Align > LD->getAlignment()) return DAG.getExtLoad(LD->getExtensionType(), N->getDebugLoc(), @@ -4904,7 +4904,7 @@ SDValue DAGCombiner::visitSTORE(SDNode *N) { SDValue Ptr = ST->getBasePtr(); // Try to infer better alignment information than the store already has. - if (!Fast && ST->isUnindexed()) { + if (OptLevel != 0 && ST->isUnindexed()) { if (unsigned Align = InferAlignment(Ptr, DAG)) { if (Align > ST->getAlignment()) return DAG.getTruncStore(Chain, N->getDebugLoc(), Value, @@ -6084,8 +6084,9 @@ SDValue DAGCombiner::FindBetterChain(SDNode *N, SDValue OldChain) { // SelectionDAG::Combine - This is the entry point for the file. // -void SelectionDAG::Combine(CombineLevel Level, AliasAnalysis &AA, bool Fast) { +void SelectionDAG::Combine(CombineLevel Level, AliasAnalysis &AA, + unsigned OptLevel) { /// run - This is the main entry point to this class. /// - DAGCombiner(*this, AA, Fast).Run(Level); + DAGCombiner(*this, AA, OptLevel).Run(Level); } diff --git a/lib/CodeGen/SelectionDAG/FastISel.cpp b/lib/CodeGen/SelectionDAG/FastISel.cpp index 12b0b12c40..a7801ebccf 100644 --- a/lib/CodeGen/SelectionDAG/FastISel.cpp +++ b/lib/CodeGen/SelectionDAG/FastISel.cpp @@ -327,7 +327,7 @@ bool FastISel::SelectCall(User *I) { default: break; case Intrinsic::dbg_stoppoint: { DbgStopPointInst *SPI = cast<DbgStopPointInst>(I); - if (DW && DW->ValidDebugInfo(SPI->getContext(), true)) { + if (DW && DW->ValidDebugInfo(SPI->getContext(), 0)) { DICompileUnit CU(cast<GlobalVariable>(SPI->getContext())); std::string Dir, FN; unsigned SrcFile = DW->getOrCreateSourceID(CU.getDirectory(Dir), @@ -344,7 +344,7 @@ bool FastISel::SelectCall(User *I) { } case Intrinsic::dbg_region_start: { DbgRegionStartInst *RSI = cast<DbgRegionStartInst>(I); - if (DW && DW->ValidDebugInfo(RSI->getContext(), true)) { + if (DW && DW->ValidDebugInfo(RSI->getContext(), 0)) { unsigned ID = DW->RecordRegionStart(cast<GlobalVariable>(RSI->getContext())); const TargetInstrDesc &II = TII.get(TargetInstrInfo::DBG_LABEL); @@ -354,7 +354,7 @@ bool FastISel::SelectCall(User *I) { } case Intrinsic::dbg_region_end: { DbgRegionEndInst *REI = cast<DbgRegionEndInst>(I); - if (DW && DW->ValidDebugInfo(REI->getContext(), true)) { + if (DW && DW->ValidDebugInfo(REI->getContext(), 0)) { unsigned ID = 0; DISubprogram Subprogram(cast<GlobalVariable>(REI->getContext())); if (!Subprogram.isNull() && !Subprogram.describes(MF.getFunction())) { @@ -380,7 +380,7 @@ bool FastISel::SelectCall(User *I) { DbgFuncStartInst *FSI = cast<DbgFuncStartInst>(I); Value *SP = FSI->getSubprogram(); - if (DW->ValidDebugInfo(SP, true)) { + if (DW->ValidDebugInfo(SP, 0)) { // llvm.dbg.func.start implicitly defines a dbg_stoppoint which is what // (most?) gdb expects. DebugLoc PrevLoc = DL; @@ -425,7 +425,7 @@ bool FastISel::SelectCall(User *I) { case Intrinsic::dbg_declare: { DbgDeclareInst *DI = cast<DbgDeclareInst>(I); Value *Variable = DI->getVariable(); - if (DW && DW->ValidDebugInfo(Variable, true)) { + if (DW && DW->ValidDebugInfo(Variable, 0)) { // Determine the address of the declared object. Value *Address = DI->getAddress(); if (BitCastInst *BCI = dyn_cast<BitCastInst>(Address)) diff --git a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp index 0b019fdeee..25305ea243 100644 --- a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp +++ b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp @@ -55,8 +55,8 @@ namespace { class VISIBILITY_HIDDEN SelectionDAGLegalize { TargetLowering &TLI; SelectionDAG &DAG; + unsigned OptLevel; bool TypesNeedLegalizing; - bool Fast; // Libcall insertion helpers. @@ -139,7 +139,7 @@ class VISIBILITY_HIDDEN SelectionDAGLegalize { public: explicit SelectionDAGLegalize(SelectionDAG &DAG, bool TypesNeedLegalizing, - bool fast); + unsigned ol); /// getTypeAction - Return how we should legalize values of this type, either /// it is already legal or we need to expand it into multiple registers of @@ -345,9 +345,9 @@ SDValue SelectionDAGLegalize::promoteShuffle(MVT NVT, MVT VT, DebugLoc dl, } SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag, - bool types, bool fast) - : TLI(dag.getTargetLoweringInfo()), DAG(dag), TypesNeedLegalizing(types), - Fast(fast), ValueTypeActions(TLI.getValueTypeActions()) { + bool types, unsigned ol) + : TLI(dag.getTargetLoweringInfo()), DAG(dag), OptLevel(ol), + TypesNeedLegalizing(types), ValueTypeActions(TLI.getValueTypeActions()) { assert(MVT::LAST_VALUETYPE <= 32 && "Too many value types for ValueTypeActions to hold!"); } @@ -1271,7 +1271,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) { unsigned Line = DSP->getLine(); unsigned Col = DSP->getColumn(); - if (Fast) { + if (OptLevel == 0) { // A bit self-referential to have DebugLoc on Debug_Loc nodes, but it // won't hurt anything. if (useDEBUG_LOC) { @@ -8566,9 +8566,9 @@ SDValue SelectionDAGLegalize::StoreWidenVectorOp(StoreSDNode *ST, // SelectionDAG::Legalize - This is the entry point for the file. // -void SelectionDAG::Legalize(bool TypesNeedLegalizing, bool Fast) { +void SelectionDAG::Legalize(bool TypesNeedLegalizing, unsigned OptLevel) { /// run - This is the main entry point to this class. /// - SelectionDAGLegalize(*this, TypesNeedLegalizing, Fast).LegalizeDAG(); + SelectionDAGLegalize(*this, TypesNeedLegalizing, OptLevel).LegalizeDAG(); } diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp index 0c343f9880..c87820a97b 100644 --- a/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp +++ b/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp @@ -630,6 +630,6 @@ void ScheduleDAGFast::ListScheduleBottomUp() { //===----------------------------------------------------------------------===// llvm::ScheduleDAGSDNodes * -llvm::createFastDAGScheduler(SelectionDAGISel *IS, bool) { +llvm::createFastDAGScheduler(SelectionDAGISel *IS, unsigned) { return new ScheduleDAGFast(*IS->MF); } diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp index e63484e987..2ac934a0d0 100644 --- a/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp +++ b/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp @@ -261,7 +261,7 @@ void ScheduleDAGList::ListScheduleTopDown() { /// new hazard recognizer. This scheduler takes ownership of the hazard /// recognizer and deletes it when done. ScheduleDAGSDNodes * -llvm::createTDListDAGScheduler(SelectionDAGISel *IS, bool Fast) { +llvm::createTDListDAGScheduler(SelectionDAGISel *IS, unsigned) { return new ScheduleDAGList(*IS->MF, new LatencyPriorityQueue(), IS->CreateTargetHazardRecognizer()); diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp index 20a081d054..aecd02aba3 100644 --- a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp +++ b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp @@ -1505,7 +1505,7 @@ bool td_ls_rr_sort::operator()(const SUnit *left, const SUnit *right) const { //===----------------------------------------------------------------------===// llvm::ScheduleDAGSDNodes * -llvm::createBURRListDAGScheduler(SelectionDAGISel *IS, bool) { +llvm::createBURRListDAGScheduler(SelectionDAGISel *IS, unsigned) { const TargetMachine &TM = IS->TM; const TargetInstrInfo *TII = TM.getInstrInfo(); const TargetRegisterInfo *TRI = TM.getRegisterInfo(); @@ -1519,7 +1519,7 @@ llvm::createBURRListDAGScheduler(SelectionDAGISel *IS, bool) { } llvm::ScheduleDAGSDNodes * -llvm::createTDRRListDAGScheduler(SelectionDAGISel *IS, bool) { +llvm::createTDRRListDAGScheduler(SelectionDAGISel *IS, unsigned) { const TargetMachine &TM = IS->TM; const TargetInstrInfo *TII = TM.getInstrInfo(); const TargetRegisterInfo *TRI = TM.getRegisterInfo(); diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp index aac4b655db..6fe56578b2 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp @@ -3910,9 +3910,9 @@ SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) { case Intrinsic::dbg_stoppoint: { DwarfWriter *DW = DAG.getDwarfWriter(); DbgStopPointInst &SPI = cast<DbgStopPointInst>(I); - if (DW && DW->ValidDebugInfo(SPI.getContext(), Fast)) { + if (DW && DW->ValidDebugInfo(SPI.getContext(), OptLevel)) { MachineFunction &MF = DAG.getMachineFunction(); - if (Fast) + if (OptLevel == 0) DAG.setRoot(DAG.getDbgStopPoint(getRoot(), SPI.getLine(), SPI.getColumn(), @@ -3930,7 +3930,8 @@ SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) { case Intrinsic::dbg_region_start: { DwarfWriter *DW = DAG.getDwarfWriter(); DbgRegionStartInst &RSI = cast<DbgRegionStartInst>(I); - if (DW && DW->ValidDebugInfo(RSI.getContext(), Fast)) { + + if (DW && DW->ValidDebugInfo(RSI.getContext(), OptLevel)) { unsigned LabelID = DW->RecordRegionStart(cast<GlobalVariable>(RSI.getContext())); DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getCurDebugLoc(), @@ -3942,8 +3943,8 @@ SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) { case Intrinsic::dbg_region_end: { DwarfWriter *DW = DAG.getDwarfWriter(); DbgRegionEndInst &REI = cast<DbgRegionEndInst>(I); - if (DW && DW->ValidDebugInfo(REI.getContext(), Fast)) { + if (DW && DW->ValidDebugInfo(REI.getContext(), OptLevel)) { MachineFunction &MF = DAG.getMachineFunction(); DISubprogram Subprogram(cast<GlobalVariable>(REI.getContext())); std::string SPName; @@ -3952,7 +3953,7 @@ SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) { && strcmp(SPName.c_str(), MF.getFunction()->getNameStart())) { // This is end of inlined function. Debugging information for // inlined function is not handled yet (only supported by FastISel). - if (Fast) { + if (OptLevel == 0) { unsigned ID = DW->RecordInlinedFnEnd(Subprogram); if (ID != 0) // Returned ID is 0 if this is unbalanced "end of inlined @@ -3978,9 +3979,9 @@ SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) { if (!DW) return 0; DbgFuncStartInst &FSI = cast<DbgFuncStartInst>(I); Value *SP = FSI.getSubprogram(); - if (SP && DW->ValidDebugInfo(SP, Fast)) { - MachineFunction &MF = DAG.getMachineFunction(); - if (Fast) { + if (SP && DW->ValidDebugInfo(SP, OptLevel)) { + MachineFunction &MF = DAG.getMachineFunction(); + if (OptLevel == 0) { // llvm.dbg.func.start implicitly defines a dbg_stoppoint which is what // (most?) gdb expects. DebugLoc PrevLoc = CurDebugLoc; @@ -4051,11 +4052,11 @@ SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) { return 0; } case Intrinsic::dbg_declare: { - if (Fast) { + if (OptLevel == 0) { DwarfWriter *DW = DAG.getDwarfWriter(); DbgDeclareInst &DI = cast<DbgDeclareInst>(I); Value *Variable = DI.getVariable(); - if (DW && DW->ValidDebugInfo(Variable, Fast)) + if (DW && DW->ValidDebugInfo(Variable, OptLevel)) DAG.setRoot(DAG.getNode(ISD::DECLARE, dl, MVT::Other, getRoot(), getValue(DI.getAddress()), getValue(Variable))); } else { diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGBuild.h b/lib/CodeGen/SelectionDAG/SelectionDAGBuild.h index ecac1ae0a2..773f33938c 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAGBuild.h +++ b/lib/CodeGen/SelectionDAG/SelectionDAGBuild.h @@ -355,17 +355,17 @@ public: /// FunctionLoweringInfo &FuncInfo; - /// Fast - We are in -fast mode. + /// OptLevel - What optimization level we're generating code for. /// - bool Fast; + unsigned OptLevel; /// GFI - Garbage collection metadata for the function. GCFunctionInfo *GFI; SelectionDAGLowering(SelectionDAG &dag, TargetLowering &tli, - FunctionLoweringInfo &funcinfo, bool fast) + FunctionLoweringInfo &funcinfo, unsigned ol) : CurDebugLoc(DebugLoc::getUnknownLoc()), - TLI(tli), DAG(dag), FuncInfo(funcinfo), Fast(fast) { + TLI(tli), DAG(dag), FuncInfo(funcinfo), OptLevel(ol) { } void init(GCFunctionInfo *gfi, AliasAnalysis &aa); diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp index 2953472da9..37087ec6d5 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp @@ -136,16 +136,16 @@ namespace llvm { /// createDefaultScheduler - This creates an instruction scheduler appropriate /// for the target. ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS, - bool Fast) { + unsigned OptLevel) { const TargetLowering &TLI = IS->getTargetLowering(); - if (Fast) - return createFastDAGScheduler(IS, Fast); + if (OptLevel == 0) + return createFastDAGScheduler(IS, OptLevel); if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency) - return createTDListDAGScheduler(IS, Fast); + return createTDListDAGScheduler(IS, OptLevel); assert(TLI.getSchedulingPreference() == TargetLowering::SchedulingForRegPressure && "Unknown sched type!"); - return createBURRListDAGScheduler(IS, Fast); + return createBURRListDAGScheduler(IS, OptLevel); } } @@ -262,13 +262,13 @@ static void EmitLiveInCopies(MachineBasicBlock *EntryMBB, // SelectionDAGISel code //===----------------------------------------------------------------------===// -SelectionDAGISel::SelectionDAGISel(TargetMachine &tm, bool fast) : +SelectionDAGISel::SelectionDAGISel(TargetMachine &tm, unsigned OL) : FunctionPass(&ID), TM(tm), TLI(*tm.getTargetLowering()), FuncInfo(new FunctionLoweringInfo(TLI)), CurDAG(new SelectionDAG(TLI, *FuncInfo)), - SDL(new SelectionDAGLowering(*CurDAG, TLI, *FuncInfo, fast)), + SDL(new SelectionDAGLowering(*CurDAG, TLI, *FuncInfo, OL)), GFI(), - Fast(fast), + OptLevel(OL), DAGSize(0) {} @@ -576,9 +576,9 @@ void SelectionDAGISel::CodeGenAndEmitDAG() { // Run the DAG combiner in pre-legalize mode. if (TimePassesIsEnabled) { NamedRegionTimer T("DAG Combining 1", GroupName); - CurDAG->Combine(Unrestricted, *AA, Fast); + CurDAG->Combine(Unrestricted, *AA, OptLevel); } else { - CurDAG->Combine(Unrestricted, *AA, Fast); + CurDAG->Combine(Unrestricted, *AA, OptLevel); } DOUT << "Optimized lowered selection DAG:\n"; @@ -608,9 +608,9 @@ void SelectionDAGISel::CodeGenAndEmitDAG() { // Run the DAG combiner in post-type-legalize mode. if (TimePassesIsEnabled) { NamedRegionTimer T("DAG Combining after legalize types", GroupName); - CurDAG->Combine(NoIllegalTypes, *AA, Fast); + CurDAG->Combine(NoIllegalTypes, *AA, OptLevel); } else { - CurDAG->Combine(NoIllegalTypes, *AA, Fast); + CurDAG->Combine(NoIllegalTypes, *AA, OptLevel); } DOUT << "Optimized type-legalized selection DAG:\n"; @@ -622,9 +622,9 @@ void SelectionDAGISel::CodeGenAndEmitDAG() { if (TimePassesIsEnabled) { NamedRegionTimer T("DAG Legalization", GroupName); - CurDAG->Legalize(DisableLegalizeTypes, Fast); + CurDAG->Legalize(DisableLegalizeTypes, OptLevel); } else { - CurDAG->Legalize(DisableLegalizeTypes, Fast); + CurDAG->Legalize(DisableLegalizeTypes, OptLevel); } DOUT << "Legalized selection DAG:\n"; @@ -635,9 +635,9 @@ void SelectionDAGISel::CodeGenAndEmitDAG() { // Run the DAG combiner in post-legalize mode. if (TimePassesIsEnabled) { NamedRegionTimer T("DAG Combining 2", GroupName); - CurDAG->Combine(NoIllegalOperations, *AA, Fast); + CurDAG->Combine(NoIllegalOperations, *AA, OptLevel); } else { - CurDAG->Combine(NoIllegalOperations, *AA, Fast); + CurDAG->Combine(NoIllegalOperations, *AA, OptLevel); } DOUT << "Optimized legalized selection DAG:\n"; @@ -645,7 +645,7 @@ void SelectionDAGISel::CodeGenAndEmitDAG() { if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName); - if (!Fast) + if (OptLevel != 0) ComputeLiveOutVRegInfo(); // Third, instruction select all of the operations to machine code, adding the @@ -1082,7 +1082,7 @@ ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() { RegisterScheduler::setDefault(Ctor); } - return Ctor(this, Fast); + return Ctor(this, OptLevel); } ScheduleHazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() { diff --git a/lib/Target/ARM/ARM.h b/lib/Target/ARM/ARM.h index fa17742016..63bb8f6073 100644 --- a/lib/Target/ARM/ARM.h +++ b/lib/Target/ARM/ARM.h @@ -91,7 +91,7 @@ inline static const char *ARMCondCodeToString(ARMCC::CondCodes CC) { FunctionPass *createARMISelDag(ARMTargetMachine &TM); FunctionPass *createARMCodePrinterPass(raw_ostream &O, ARMTargetMachine &TM, - bool Fast, bool Verbose); + unsigned OptLevel, bool Verbose); FunctionPass *createARMCodeEmitterPass(ARMTargetMachine &TM, MachineCodeEmitter &MCE); FunctionPass *createARMLoadStoreOptimizationPass(); diff --git a/lib/Target/ARM/ARMTargetMachine.cpp b/lib/Target/ARM/ARMTargetMachine.cpp index 9b6e51267f..a2ee52e30d 100644 --- a/lib/Target/ARM/ARMTargetMachine.cpp +++ b/lib/Target/ARM/ARMTargetMachine.cpp @@ -138,35 +138,37 @@ const TargetAsmInfo *ARMTargetMachine::createTargetAsmInfo() const { // Pass Pipeline Configuration -bool ARMTargetMachine::addInstSelector(PassManagerBase &PM, bool Fast) { +bool ARMTargetMachine::addInstSelector(PassManagerBase &PM, unsigned OptLevel) { PM.add(createARMISelDag(*this)); return false; } -bool ARMTargetMachine::addPreEmitPass(PassManagerBase &PM, bool Fast) { +bool ARMTargetMachine::addPreEmitPass(PassManagerBase &PM, unsigned OptLevel) { // FIXME: temporarily disabling load / store optimization pass for Thumb mode. - if (!Fast && !DisableLdStOpti && !Subtarget.isThumb()) + if (OptLevel != 0 && !DisableLdStOpti && !Subtarget.isThumb()) PM.add(createARMLoadStoreOptimizationPass()); - if (!Fast && !DisableIfConversion && !Subtarget.isThumb()) + if (OptLevel != 0 && !DisableIfConversion && !Subtarget.isThumb()) PM.add(createIfConverterPass()); PM.add(createARMConstantIslandPass()); return true; } -bool ARMTargetMachine::addAssemblyEmitter(PassManagerBase &PM, bool Fast, - bool Verbose, raw_ostream &Out) { +bool ARMTargetMachine::addAssemblyEmitter(PassManagerBase &PM, + unsigned OptLevel, + bool Verbose, + raw_ostream &Out) { // Output assembly language. assert(AsmPrinterCtor && "AsmPrinter was not linked in"); if (AsmPrinterCtor) - PM.add(AsmPrinterCtor(Out, *this, Fast, Verbose)); + PM.add(AsmPrinterCtor(Out, *this, OptLevel, Verbose)); return false; } -bool ARMTargetMachine::addCodeEmitter(PassManagerBase &PM, bool Fast, +bool ARMTargetMachine::addCodeEmitter(PassManagerBase &PM, unsigned OptLevel, bool DumpAsm, MachineCodeEmitter &MCE) { // FIXME: Move this to TargetJITInfo! if (DefRelocModel == Reloc::Default) @@ -177,20 +179,22 @@ bool ARMTargetMachine::addCodeEmitter(PassManagerBase &PM, bool Fast, if (DumpAsm) { assert(AsmPrinterCtor && "AsmPrinter was not linked in"); if (AsmPrinterCtor) - PM.add(AsmPrinterCtor(errs(), *this, Fast, true)); + PM.add(AsmPrinterCtor(errs(), *this, OptLevel, true)); } return false; } -bool ARMTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM, bool Fast, - bool DumpAsm, MachineCodeEmitter &MCE) { +bool ARMTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM, + unsigned OptLevel, + bool DumpAsm, + MachineCodeEmitter &MCE) { // Machine code emitter pass for ARM. PM.add(createARMCodeEmitterPass(*this, MCE)); if (DumpAsm) { assert(AsmPrinterCtor && "AsmPrinter was not linked in"); if (AsmPrinterCtor) - PM.add(AsmPrinterCtor(errs(), *this, Fast, true)); + PM.add(AsmPrinterCtor(errs(), *this, OptLevel, true)); } return false; diff --git a/lib/Target/ARM/ARMTargetMachine.h b/lib/Target/ARM/ARMTargetMachine.h index 9a3d7ed5fe..cfb617867d 100644 --- a/lib/Target/ARM/ARMTargetMachine.h +++ b/lib/Target/ARM/ARMTargetMachine.h @@ -41,7 +41,7 @@ protected: // set this functions to ctor pointer at startup time if they are linked in. typedef FunctionPass *(*AsmPrinterCtorFn)(raw_ostream &o, ARMTargetMachine &tm, - bool fast, bool verbose); + unsigned OptLevel, bool verbose); static AsmPrinterCtorFn AsmPrinterCtor; public: @@ -69,13 +69,13 @@ public: virtual const TargetAsmInfo *createTargetAsmInfo() const; // Pass Pipeline Configuration - virtual bool addInstSelector(PassManagerBase &PM, bool Fast); - virtual bool addPreEmitPass(PassManagerBase &PM, bool Fast); - virtual bool addAssemblyEmitter(PassManagerBase &PM, bool Fast, + virtual bool addInstSelector(PassManagerBase &PM, unsigned OptLevel); + virtual bool addPreEmitPass(PassManagerBase &PM, unsigned OptLevel); + virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel, bool Verbose, raw_ostream &Out); - virtual bool addCodeEmitter(PassManagerBase &PM, bool Fast, + virtual bool addCodeEmitter(PassManagerBase &PM, unsigned OptLevel, bool DumpAsm, MachineCodeEmitter &MCE); - virtual bool addSimpleCodeEmitter(PassManagerBase &PM, bool Fast, + virtual bool addSimpleCodeEmitter(PassManagerBase &PM, unsigned OptLevel, bool DumpAsm, MachineCodeEmitter &MCE); }; diff --git a/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp b/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp index b3fa88eeaa..6559a9d797 100644 --- a/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp +++ b/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp @@ -80,9 +80,9 @@ namespace { /// True if asm printer is printing a series of CONSTPOOL_ENTRY. bool InCPMode; public: - ARMAsmPrinter(raw_ostream &O, TargetMachine &TM, - const TargetAsmInfo *T, bool F, bool V) - : AsmPrinter(O, TM, T, F, V), DW(0), MMI(NULL), AFI(NULL), MCP(NULL), + explicit ARMAsmPrinter(raw_ostream &O, TargetMachine &TM, + const TargetAsmInfo *T, unsigned OL, bool V) + : AsmPrinter(O, TM, T, OL, V), DW(0), MMI(NULL), AFI(NULL), MCP(NULL), InCPMode(false) { Subtarget = &TM.getSubtarget<ARMSubtarget>(); } @@ -1061,8 +1061,8 @@ bool ARMAsmPrinter::doFinalization(Module &M) { /// FunctionPass *llvm::createARMCodePrinterPass(raw_ostream &o, ARMTargetMachine &tm, - bool fast, bool verbose) { - return new ARMAsmPrinter(o, tm, tm.getTargetAsmInfo(), fast, verbose); + unsigned OptLevel, bool verbose) { + return new ARMAsmPrinter(o, tm, tm.getTargetAsmInfo(), OptLevel, verbose); } namespace { diff --git a/lib/Target/Alpha/Alpha.h b/lib/Target/Alpha/Alpha.h index d93394aa6f..994edaa24c 100644 --- a/lib/Target/Alpha/Alpha.h +++ b/lib/Target/Alpha/Alpha.h @@ -26,7 +26,7 @@ namespace llvm { FunctionPass *createAlphaISelDag(AlphaTargetMachine &TM); FunctionPass *createAlphaCodePrinterPass(raw_ostream &OS, TargetMachine &TM, - bool Fast, bool Verbose); + unsigned OptLevel, bool Verbose); FunctionPass *createAlphaPatternInstructionSelector(TargetMachine &TM); FunctionPass *createAlphaCodeEmitterPass(AlphaTargetMachine &TM, MachineCodeEmitter &MCE); diff --git a/lib/Target/Alpha/AlphaTargetMachine.cpp b/lib/Target/Alpha/AlphaTargetMachine.cpp index cae91d8c4e..7a87612038 100644 --- a/lib/Target/Alpha/AlphaTargetMachine.cpp +++ b/lib/Target/Alpha/AlphaTargetMachine.cpp @@ -76,31 +76,34 @@ AlphaTargetMachine::AlphaTargetMachine(const Module &M, const std::string &FS) // Pass Pipeline Configuration //===----------------------------------------------------------------------===// -bool AlphaTargetMachine::addInstSelector(PassManagerBase &PM, bool Fast) { +bool AlphaTargetMachine::addInstSelector(PassManagerBase &PM, + unsigned OptLevel) { PM.add(createAlphaISelDag(*this)); return false; } -bool AlphaTargetMachine::addPreEmitPass(PassManagerBase &PM, bool Fast) { +bool AlphaTargetMachine::addPreEmitPass(PassManagerBase &PM, + unsigned OptLevel) { // Must run branch selection immediately preceding the asm printer PM.add(createAlphaBranchSelectionPass()); return false; } -bool AlphaTargetMachine::addAssemblyEmitter(PassManagerBase &PM, bool Fast, +bool AlphaTargetMachine::addAssemblyEmitter(PassManagerBase &PM, + unsigned OptLevel, bool Verbose, raw_ostream &Out) { PM.add(createAlphaLLRPPass(*this)); - PM.add(createAlphaCodePrinterPass(Out, *this, Fast, Verbose)); + PM.add(createAlphaCodePrinterPass(Out, *this, OptLevel, Verbose)); return false; } -bool AlphaTargetMachine::addCodeEmitter(PassManagerBase &PM, bool Fast, +bool AlphaTargetMachine::addCodeEmitter(PassManagerBase &PM, unsigned OptLevel, bool DumpAsm, MachineCodeEmitter &MCE) { PM.add(createAlphaCodeEmitterPass(*this, MCE)); if (DumpAsm) - PM.add(createAlphaCodePrinterPass(errs(), *this, Fast, true)); + PM.add(createAlphaCodePrinterPass(errs(), *this, OptLevel, true)); return false; } bool AlphaTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM, - bool Fast, bool DumpAsm, + unsigned OptLevel, bool DumpAsm, MachineCodeEmitter &MCE) { - return addCodeEmitter(PM, Fast, DumpAsm, MCE); + return addCodeEmitter(PM, OptLevel, DumpAsm, MCE); } diff --git a/lib/Target/Alpha/AlphaTargetMachine.h b/lib/Target/Alpha/AlphaTargetMachine.h index 9a03baef3f..309c2e8877 100644 --- a/lib/Target/Alpha/AlphaTargetMachine.h +++ b/lib/Target/Alpha/AlphaTargetMachine.h @@ -58,13 +58,13 @@ public: static unsigned getModuleMatchQuality(const Module &M); // Pass Pipeline Configuration - virtual bool addInstSelector(PassManagerBase &PM, bool Fast); - virtual bool addPreEmitPass(PassManagerBase &PM, bool Fast); - virtual bool addAssemblyEmitter(PassManagerBase &PM, bool Fast, + virtual bool addInstSelector(PassManagerBase &PM, unsigned OptLevel); + virtual bool addPreEmitPass(PassManagerBase &PM, unsigned OptLevel); + virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel, bool Verbose, raw_ostream &Out); - virtual bool addCodeEmitter(PassManagerBase &PM, bool Fast, + virtual bool addCodeEmitter(PassManagerBase &PM, unsigned OptLevel, bool DumpAsm, MachineCodeEmitter &MCE); - virtual bool addSimpleCodeEmitter(PassManagerBase &PM, bool Fast, + virtual bool addSimpleCodeEmitter(PassManagerBase &PM, unsigned OptLevel, bool DumpAsm, MachineCodeEmitter &MCE); }; diff --git a/lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp b/lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp index 0df7e809af..292a380595 100644 --- a/lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp +++ b/lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp @@ -36,9 +36,9 @@ namespace { /// Unique incrementer for label values for referencing Global values. /// - AlphaAsmPrinter(raw_ostream &o, TargetMachine &tm, - const TargetAsmInfo *T, bool F, bool V) - : AsmPrinter(o, tm, T, F, V) {} + explicit AlphaAsmPrinter(raw_ostream &o, TargetMachine &tm, + const TargetAsmInfo *T, unsigned OL, bool V) + : AsmPrinter(o, tm, T, OL, V) {} virtual const char *getPassName() const { return "Alpha Assembly Printer"; @@ -68,8 +68,9 @@ namespace { /// FunctionPass *llvm::createAlphaCodePrinterPass(raw_ostream &o, TargetMachine &tm, - bool fast, bool verbose) { - return new AlphaAsmPrinter(o, tm, tm.getTargetAsmInfo(), fast, verbose); + unsigned OptLevel, + bool verbose) { + return new AlphaAsmPrinter(o, tm, tm.getTargetAsmInfo(), OptLevel, verbose); } #include "AlphaGenAsmWriter.inc" diff --git a/lib/Target/CBackend/CBackend.cpp b/lib/Target/CBackend/CBackend.cpp index 8b2473b1ba..0a8e9df523 100644 --- a/lib/Target/CBackend/CBackend.cpp +++ b/lib/Target/CBackend/CBackend.cpp @@ -3587,7 +3587,7 @@ void CWriter::visitExtractValueInst(ExtractValueInst &EVI) { bool CTargetMachine::addPassesToEmitWholeFile(PassManager &PM, raw_ostream &o, CodeGenFileType FileType, - bool Fast) { + unsigned OptLevel) { if (FileType != TargetMachine::AssemblyFile) return true; PM.add(createGCLoweringPass()); diff --git a/lib/Target/CBackend/CTargetMachine.h b/lib/Target/CBackend/CTargetMachine.h index a17df05025..a851486a20 100644 --- a/lib/Target/CBackend/CTargetMachine.h +++ b/lib/Target/CBackend/CTargetMachine.h @@ -27,7 +27,8 @@ struct CTargetMachine : public TargetMachine { virtual bool WantsWholeFile() const { return true; } virtual bool addPassesToEmitWholeFile(PassManager &PM, raw_ostream &Out, - CodeGenFileType FileType, bool Fast); + CodeGenFileType FileType, + unsigned OptLevel); // This class always works, but must be requested explicitly on // llc command line. diff --git a/lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp b/lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp index 788f737f35..6e77c87e6f 100644 --- a/lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp +++ b/lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp @@ -48,9 +48,9 @@ namespace { class VISIBILITY_HIDDEN SPUAsmPrinter : public AsmPrinter { std::set<std::string> FnStubs, GVStubs; public: - SPUAsmPrinter(raw_ostream &O, TargetMachine &TM, - const TargetAsmInfo *T, bool F, bool V) : - AsmPrinter(O, TM, T, F, V) {} + explicit SPUAsmPrinter(raw_ostream &O, TargetMachine &TM, + const TargetAsmInfo *T, unsigned OL, bool V) : + AsmPrinter(O, TM, T, OL, V) {} virtual const char *getPassName() const { return "STI CBEA SPU Assembly Printer"; @@ -615,6 +615,6 @@ bool LinuxAsmPrinter::doFinalization(Module &M) { /// FunctionPass *llvm::createSPUAsmPrinterPass(raw_ostream &o, SPUTargetMachine &tm, - bool fast, bool verbose) { - return new LinuxAsmPrinter(o, tm, tm.getTargetAsmInfo(), fast, verbose); + unsigned OptLevel, bool verbose) { + return new LinuxAsmPrinter(o, tm, tm.getTargetAsmInfo(), OptLevel, verbose); } diff --git a/lib/Target/CellSPU/SPU.h b/lib/Target/CellSPU/SPU.h index 9bb199a16e..5c62bc3a42 100644 --- a/lib/Target/CellSPU/SPU.h +++ b/lib/Target/CellSPU/SPU.h @@ -25,7 +25,7 @@ namespace llvm { FunctionPass *createSPUISelDag(SPUTargetMachine &TM); FunctionPass *createSPUAsmPrinterPass(raw_ostream &o, SPUTargetMachine &tm, - bool fast, bool verbose); + unsigned OptLevel, bool verbose); /*--== Utility functions/predicates/etc used all over the place: --==*/ //! Predicate test for a signed 10-bit value diff --git a/lib/Target/CellSPU/SPUTargetMachine.cpp b/lib/Target/CellSPU/SPUTargetMachine.cpp index 5e69927356..c8cf3643f5 100644 --- a/lib/Target/CellSPU/SPUTargetMachine.cpp +++ b/lib/Target/CellSPU/SPUTargetMachine.cpp @@ -81,15 +81,17 @@ SPUTargetMachine::SPUTargetMachine(const Module &M, const std::string &FS) //===----------------------------------------------------------------------===// bool -SPUTargetMachine::addInstSelector(PassManagerBase &PM, bool Fast) +SPUTargetMachine::addInstSelector(PassManagerBase &PM, unsigned OptLevel) { // Install an instruction selector. PM.add(createSPUISelDag(*this)); return false; } -bool SPUTargetMachine::addAssemblyEmitter(PassManagerBase &PM, bool Fast, - bool Verbose, raw_ostream &Out) { - PM.add(createSPUAsmPrinterPass(Out, *this, Fast, Verbose)); +bool SPUTargetMachine::addAssemblyEmitter(PassManagerBase &PM, + unsigned OptLevel, + bool Verbose, + raw_ostream &Out) { + PM.add(createSPUAsmPrinterPass(Out, *this, OptLevel, Verbose)); return false; } diff --git a/lib/Target/CellSPU/SPUTargetMachine.h b/lib/Target/CellSPU/SPUTargetMachine.h index 32eb7f2342..e959e9187b 100644 --- a/lib/Target/CellSPU/SPUTargetMachine.h +++ b/lib/Target/CellSPU/SPUTargetMachine.h @@ -83,9 +83,9 @@ public: } // Pass Pipeline Configuration - virtual bool addInstSelector(PassManagerBase &PM, bool /*Fast*/); - virtual bool addAssemblyEmitter(PassManagerBase &PM, bool /*Fast*/, - bool /*Verbose*/, raw_ostream &Out); + virtual bool addInstSelector(PassManagerBase &PM, unsigned OptLevel); + virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel, + bool Verbose, raw_ostream &Out); }; } // end namespace llvm diff --git a/lib/Target/CppBackend/CPPBackend.cpp b/lib/Target/CppBackend/CPPBackend.cpp index e89d5f9ddd..3d6362145e 100644 --- a/lib/Target/CppBackend/CPPBackend.cpp +++ b/lib/Target/CppBackend/CPPBackend.cpp @@ -1995,7 +1995,7 @@ char CppWriter::ID = 0; bool CPPTargetMachine::addPassesToEmitWholeFile(PassManager &PM, raw_ostream &o, CodeGenFileType FileType, - bool Fast) { + unsigned OptLevel) { if (FileType != TargetMachine::AssemblyFile) return true; PM.add(new CppWriter(o)); return false; diff --git a/lib/Target/CppBackend/CPPTargetMachine.h b/lib/Target/CppBackend/CPPTargetMachine.h index db17c17826..90b8268888 100644 --- a/lib/Target/CppBackend/CPPTargetMachine.h +++ b/lib/Target/CppBackend/CPPTargetMachine.h @@ -29,7 +29,8 @@ struct CPPTargetMachine : public TargetMachine { virtual bool WantsWholeFile() const { return true; } virtual bool addPassesToEmitWholeFile(PassManager &PM, raw_ostream &Out, - CodeGenFileType FileType, bool Fast); + CodeGenFileType FileType, + unsigned OptLevel); // This class always works, but shouldn't be the default in most cases. static unsigned getModuleMatchQuality(const Module &M) { return 1; } diff --git a/lib/Target/IA64/AsmPrinter/IA64AsmPrinter.cpp b/lib/Target/IA64/AsmPrinter/IA64AsmPrinter.cpp index 2e9f5e67c0..5fd8811285 100644 --- a/lib/Target/IA64/AsmPrinter/IA64AsmPrinter.cpp +++ b/lib/Target/IA64/AsmPrinter/IA64AsmPrinter.cpp @@ -37,9 +37,9 @@ namespace { class IA64AsmPrinter : public AsmPrinter { std::set<std::string> ExternalFunctionNames, ExternalObjectNames; public: - IA64AsmPrinter(raw_ostream &O, TargetMachine &TM, - const TargetAsmInfo *T, bool F, bool V) - : AsmPrinter(O, TM, T, F, V) {} + explicit IA64AsmPrinter(raw_ostream &O, TargetMachine &TM, + const TargetAsmInfo *T, unsigned OL, bool V) + : AsmPrinter(O, TM, T, OL, V) {} virtual const char *getPassName() const { return "IA64 Assembly Printer"; @@ -370,6 +370,7 @@ bool IA64AsmPrinter::doFinalization(Module &M) { /// FunctionPass *llvm::createIA64CodePrinterPass(raw_ostream &o, IA64TargetMachine &tm, - bool fast, bool verbose) { - return new IA64AsmPrinter(o, tm, tm.getTargetAsmInfo(), fast, verbose); + unsigned OptLevel, + bool verbose) { + return new IA64AsmPrinter(o, tm, tm.getTargetAsmInfo(), OptLevel, verbose); } diff --git a/lib/Target/IA64/IA64.h b/lib/Target/IA64/IA64.h index 9b31e258a2..46c26f0a5a 100644 --- a/lib/Target/IA64/IA64.h +++ b/lib/Target/IA64/IA64.h @@ -37,7 +37,7 @@ FunctionPass *createIA64BundlingPass(IA64TargetMachine &TM); /// FunctionPass *createIA64CodePrinterPass(raw_ostream &o, IA64TargetMachine &tm, - bool fast, bool verbose); + unsigned OptLevel, bool verbose); } // End llvm namespace diff --git a/lib/Target/IA64/IA64TargetMachine.cpp b/lib/Target/IA64/IA64TargetMachine.cpp index 58ae27a75e..c472657c6e 100644 --- a/lib/Target/IA64/IA64TargetMachine.cpp +++ b/lib/Target/IA64/IA64TargetMachine.cpp @@ -72,19 +72,21 @@ IA64TargetMachine::IA64TargetMachine(const Module &M, const std::string &FS) // Pass Pipeline Configuration //===----------------------------------------------------------------------===// -bool IA64TargetMachine::addInstSelector(PassManagerBase &PM, bool Fast) { +bool IA64TargetMachine::addInstSelector(PassManagerBase &PM, unsigned OptLEvel){ PM.add(createIA64DAGToDAGInstructionSelector(*this)); return false; } -bool IA64TargetMachine::addPreEmitPass(PassManagerBase &PM, bool Fast) { +bool IA64TargetMachine::addPreEmitPass(PassManagerBase &PM, unsigned OptLevel) { // Make sure everything is bundled happily PM.add(createIA64BundlingPass(*this)); return true; } -bool IA64TargetMachine::addAssemblyEmitter(PassManagerBase &PM, bool Fast, - bool Verbose, raw_ostream &Out) { - PM.add(createIA64CodePrinterPass(Out, *this, Fast, Verbose)); +bool IA64TargetMachine::addAssemblyEmitter(PassManagerBase &PM, + unsigned OptLevel, + bool Verbose, + raw_ostream &Out) { + PM.add(createIA64CodePrinterPass(Out, *this, OptLevel, Verbose)); return false; } diff --git a/lib/Target/IA64/IA64TargetMachine.h b/lib/Target/IA64/IA64TargetMachine.h index 2066e698ae..1fbba02da3 100644 --- a/lib/Target/IA64/IA64TargetMachine.h +++ b/lib/Target/IA64/IA64TargetMachine.h @@ -51,9 +51,9 @@ public: static unsigned getModuleMatchQuality(const Module &M); // Pass Pipeline Configuration - virtual bool addInstSelector(PassManagerBase &PM, bool Fast); - virtual bool addPreEmitPass(PassManagerBase &PM, bool Fast); - virtual bool addAssemblyEmitter(PassManagerBase &PM, bool Fast, + virtual bool addInstSelector(PassManagerBase &PM, unsigned OptLevel); + virtual bool addPreEmitPass(PassManagerBase &PM, unsigned OptLevel); + virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel, bool Verbose, raw_ostream &Out); }; } // End llvm namespace diff --git a/lib/Target/MSIL/MSILWriter.cpp b/lib/Target/MSIL/MSILWriter.cpp index 6b572f35a5..8d9a1ea7ed 100644 --- a/lib/Target/MSIL/MSILWriter.cpp +++ b/lib/Target/MSIL/MSILWriter.cpp @@ -35,7 +35,8 @@ namespace { virtual bool WantsWholeFile() const { return true; } virtual bool addPassesToEmitWholeFile(PassManager &PM, raw_ostream &Out, - CodeGenFileType FileType, bool Fast); + CodeGenFileType FileType, + unsigned OptLevel); // This class always works, but shouldn't be the default in most cases. static unsigned getModuleMatchQuality(const Module &M) { return 1; } @@ -1662,7 +1663,8 @@ void MSILWriter::printExternals() { //===----------------------------------------------------------------------===// bool MSILTarget::addPassesToEmitWholeFile(PassManager &PM, raw_ostream &o, - CodeGenFileType FileType, bool Fast) + CodeGenFileType FileType, + unsigned OptLevel) { if (FileType != TargetMachine::AssemblyFile) return true; MSILWriter* Writer = new MSILWriter(o); diff --git a/lib/Target/Mips/AsmPrinter/MipsAsmPrinter.cpp b/lib/Target/Mips/AsmPrinter/MipsAsmPrinter.cpp index 532c82df06..6692f2e40a 100644 --- a/lib/Target/Mips/AsmPrinter/MipsAsmPrinter.cpp +++ b/lib/Target/Mips/AsmPrinter/MipsAsmPrinter.cpp @@ -49,9 +49,9 @@ namespace { class VISIBILITY_HIDDEN MipsAsmPrinter : public AsmPrinter { const MipsSubtarget *Subtarget; public: - MipsAsmPrinter(raw_ostream &O, MipsTargetMachine &TM, - const TargetAsmInfo *T, bool F, bool V) - : AsmPrinter(O, TM, T, F, V) { + explicit MipsAsmPrinter(raw_ostream &O, MipsTargetMachine &TM, + const TargetAsmInfo *T, unsigned OL, bool V) + : AsmPrinter(O, TM, T, OL, V) { Subtarget = &TM.getSubtarget<MipsSubtarget>(); } @@ -91,8 +91,8 @@ namespace { /// regardless of whether the function is in SSA form. FunctionPass *llvm::createMipsCodePrinterPass(raw_ostream &o, MipsTargetMachine &tm, - bool fast, bool verbose) { - return new MipsAsmPrinter(o, tm, tm.getTargetAsmInfo(), fast, verbose); + unsigned OptLevel, bool verbose) { + return new MipsAsmPrinter(o, tm, tm.getTargetAsmInfo(), OptLevel, verbose); } //===----------------------------------------------------------------------===// diff --git a/lib/Target/Mips/Mips.h b/lib/Target/Mips/Mips.h index e6e4c85286..abcb9c44fa 100644 --- a/lib/Target/Mips/Mips.h +++ b/lib/Target/Mips/Mips.h @@ -25,7 +25,7 @@ namespace llvm { FunctionPass *createMipsDelaySlotFillerPass(MipsTargetMachine &TM); FunctionPass *createMipsCodePrinterPass(raw_ostream &OS, MipsTargetMachine &TM, - bool Fast, bool Verbose); + unsigned OptLevel, bool Verbose); } // end namespace llvm; // Defines symbolic names for Mips registers. This defines a mapping from diff --git a/lib/Target/Mips/MipsTargetMachine.cpp b/lib/Target/Mips/MipsTargetMachine.cpp index c4364a33d8..69a480deab 100644 --- a/lib/Target/Mips/MipsTargetMachine.cpp +++ b/lib/Target/Mips/MipsTargetMachine.cpp @@ -105,7 +105,7 @@ getModuleMatchQuality(const Module &M) // Install an instruction selector pass using // the ISelDag to gen Mips code. bool MipsTargetMachine:: -addInstSelector(PassManagerBase &PM, bool Fast) +addInstSelector(PassManagerBase &PM, unsigned OptLevel) { PM.add(createMipsISelDag(*this)); return false; @@ -115,7 +115,7 @@ addInstSelector(PassManagerBase &PM, bool Fast) // machine code is emitted. return true if -print-machineinstrs should // print out the code after the passes. bool MipsTargetMachine:: -addPreEmitPass(PassManagerBase &PM, bool Fast) +addPreEmitPass(PassManagerBase &PM, unsigned OptLevel) { PM.add(createMipsDelaySlotFillerPass(*this)); return true; @@ -124,10 +124,10 @@ addPreEmitPass(PassManagerBase &PM, bool Fast) // Implements the AssemblyEmitter for the target. Must return // true if AssemblyEmitter is supported bool MipsTargetMachine:: -addAssemblyEmitter(PassManagerBase &PM, bool Fast, +addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel, bool Verbose, raw_ostream &Out) { // Output assembly language. - PM.add(createMipsCodePrinterPass(Out, *this, Fast, Verbose)); + PM.add(createMipsCodePrinterPass(Out, *this, OptLevel, Verbose)); return false; } diff --git a/lib/Target/Mips/MipsTargetMachine.h b/lib/Target/Mips/MipsTargetMachine.h index 95f8e023b5..b5dc058e9e 100644 --- a/lib/Target/Mips/MipsTargetMachine.h +++ b/lib/Target/Mips/MipsTargetMachine.h @@ -57,9 +57,9 @@ namespace llvm { static unsigned getModuleMatchQuality(const Module &M); // Pass Pipeline Configuration - virtual bool addInstSelector(PassManagerBase &PM, bool Fast); - virtual bool addPreEmitPass(PassManagerBase &PM, bool Fast); - virtual bool addAssemblyEmitter(PassManagerBase &PM, bool Fast, + virtual bool addInstSelector(PassManagerBase &PM, unsigned OptLevel); + virtual bool addPreEmitPass(PassManagerBase &PM, unsigned OptLevel); + virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel, bool Verbose, raw_ostream &Out); }; diff --git a/lib/Target/PIC16/PIC16.h b/lib/Target/PIC16/PIC16.h index 786081dc1d..695fe84aca 100644 --- a/lib/Target/PIC16/PIC16.h +++ b/lib/Target/PIC16/PIC16.h @@ -75,7 +75,7 @@ namespace PIC16CC { FunctionPass *createPIC16ISelDag(PIC16TargetMachine &TM); FunctionPass *createPIC16CodePrinterPass(raw_ostream &OS, PIC16TargetMachine &TM, - bool Fast, bool Verbose); + unsigned OptLevel, bool Verbose); } // end namespace llvm; // Defines symbolic names for PIC16 registers. This defines a mapping from diff --git a/lib/Target/PIC16/PIC16AsmPrinter.cpp b/lib/Target/PIC16/PIC16AsmPrinter.cpp index 549e2d9b47..a10fcd40b0 100644 --- a/lib/Target/PIC16/PIC16AsmPrinter.cpp +++ b/lib/Target/PIC16/PIC16AsmPrinter.cpp @@ -161,8 +161,9 @@ bool PIC16AsmPrinter::runOnMachineFunction(MachineFunction &MF) { /// FunctionPass *llvm::createPIC16CodePrinterPass(raw_ostream &o, PIC16TargetMachine &tm, - bool fast, bool verbose) { - return new PIC16AsmPrinter(o, tm, tm.getTargetAsmInfo(), fast, verbose); + unsigned OptLevel, + bool verbose) { + return new PIC16AsmPrinter(o, tm, tm.getTargetAsmInfo(), OptLevel, verbose); } void PIC16AsmPrinter::printOperand(const MachineInstr *MI, int opNum) { diff --git a/lib/Target/PIC16/PIC16AsmPrinter.h b/lib/Target/PIC16/PIC16AsmPrinter.h index d9f81bd991..67eca1f590 100644 --- a/lib/Target/PIC16/PIC16AsmPrinter.h +++ b/lib/Target/PIC16/PIC16AsmPrinter.h @@ -24,9 +24,9 @@ namespace llvm { struct VISIBILITY_HIDDEN PIC16AsmPrinter : public AsmPrinter { - PIC16AsmPrinter(raw_ostream &O, PIC16TargetMachine &TM, - const TargetAsmInfo *T, bool F, bool V) - : AsmPrinter(O, TM, T, F, V) { + explicit PIC16AsmPrinter(raw_ostream &O, PIC16TargetMachine &TM, + const TargetAsmInfo *T, unsigned OL, bool V) + : AsmPrinter(O, TM, T, OL, V) { CurBank = ""; FunctionLabelBegin = '@'; IsRomData = false; diff --git a/lib/Target/PIC16/PIC16TargetMachine.cpp b/lib/Target/PIC16/PIC16TargetMachine.cpp index a8d92490e7..adc2120a40 100644 --- a/lib/Target/PIC16/PIC16TargetMachine.cpp +++ b/lib/Target/PIC16/PIC16TargetMachine.cpp @@ -55,17 +55,18 @@ const TargetAsmInfo *PIC16TargetMachine::createTargetAsmInfo() const { return new PIC16TargetAsmInfo(*this); } -bool PIC16TargetMachine::addInstSelector(PassManagerBase &PM, bool Fast) { +bool PIC16TargetMachine::addInstSelector(PassManagerBase &PM, + unsigned OptLevel) { // Install an instruction selector. PM.add(createPIC16ISelDag(*this)); return false; } bool PIC16TargetMachine:: -addAssemblyEmitter(PassManagerBase &PM, bool Fast, bool Verbose, +addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel, bool Verbose, raw_ostream &Out) { // Output assembly language. - PM.add(createPIC16CodePrinterPass(Out, *this, Fast, Verbose)); + PM.add(createPIC16CodePrinterPass(Out, *this, OptLevel, Verbose)); return false; } diff --git a/lib/Target/PIC16/PIC16TargetMachine.h b/lib/Target/PIC16/PIC16TargetMachine.h index 0ac358f0bd..b6b5d31848 100644 --- a/lib/Target/PIC16/PIC16TargetMachine.h +++ b/lib/Target/PIC16/PIC16TargetMachine.h @@ -57,8 +57,8 @@ public: return const_cast<PIC16TargetLowering*>(&TLInfo); } - virtual bool addInstSelector(PassManagerBase &PM, bool Fast); - virtual bool addAssemblyEmitter(PassManagerBase &PM, bool Fast, + virtual bool addInstSelector(PassManagerBase &PM, unsigned OptLevel); + virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel, bool Verbose, raw_ostream &Out); }; // PIC16TargetMachine. diff --git a/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp b/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp index 5b68062ab1..c690982751 100644 --- a/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp +++ b/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp @@ -54,9 +54,9 @@ namespace { StringSet<> FnStubs, GVStubs, HiddenGVStubs; const PPCSubtarget &Subtarget; public: - PPCAsmPrinter(raw_ostream &O, TargetMachine &TM, - const TargetAsmInfo *T, bool F, bool V) - : AsmPrinter(O, TM, T, F, V), + explicit PPCAsmPrinter(raw_ostream &O, TargetMachine &TM, + const TargetAsmInfo *T, unsigned OL, bool V) + : AsmPrinter(O, TM, T, OL, V), Subtarget(TM.getSubtarget<PPCSubtarget>()) {} virtual const char *getPassName() const { @@ -297,9 +297,9 @@ namespace { DwarfWriter *DW; MachineModuleInfo *MMI; public: - PPCLinuxAsmPrinter(raw_ostream &O, PPCTargetMachine &TM, - const TargetAsmInfo *T, bool F, bool V) - : PPCAsmPrinter(O, TM, T, F, V), DW(0), MMI(0) {} + explicit PPCLinuxAsmPrinter(raw_ostream &O, PPCTargetMachine &TM, + const TargetAsmInfo *T, unsigned OL, bool V) + : PPCAsmPrinter(O, TM, T, OL, V), DW(0), MMI(0) {} virtual const char *getPassName() const { return "Linux PPC Assembly Printer"; @@ -326,9 +326,9 @@ namespace { MachineModuleInfo *MMI; raw_ostream &OS; public: - PPCDarwinAsmPrinter(raw_ostream &O, PPCTargetMachine &TM, - const TargetAsmInfo *T, bool F, bool V) - : PPCAsmPrinter(O, TM, T, F, V), DW(0), MMI(0), OS(O) {} + explicit PPCDarwinAsmPrinter(raw_ostream &O, PPCTargetMachine &TM, + const TargetAsmInfo *T, unsigned OL, bool V) + : PPCAsmPrinter(O, TM, T, OL, V), DW(0), MMI(0), OS(O) {} virtual const char *getPassName() const { return "Darwin PPC Assembly Printer"; @@ -1176,13 +1176,15 @@ bool PPCDarwinAsmPrinter::doFinalization(Module &M) { /// FunctionPass *llvm::createPPCAsmPrinterPass(raw_ostream &o, PPCTargetMachine &tm, - bool fast, bool verbose) { + unsigned OptLevel, bool verbose) { const PPCSubtarget *Subtarget = &tm.getSubtarget<PPCSubtarget>(); if (Subtarget->isDarwin()) { - return new PPCDarwinAsmPrinter(o, tm, tm.getTargetAsmInfo(), fast, verbose); + return new PPCDarwinAsmPrinter(o, tm, tm.getTargetAsmInfo(), + OptLevel, verbose); } else { - return new PPCLinuxAsmPrinter(o, tm, tm.getTargetAsmInfo(), fast, verbose); + return new PPCLinuxAsmPrinter(o, tm, tm.getTargetAsmInfo(), + OptLevel, verbose); } } diff --git a/lib/Target/PowerPC/PPC.h b/lib/Target/PowerPC/PPC.h index 3ffb680fdc..f5507c29be 100644 --- a/lib/Target/PowerPC/PPC.h +++ b/lib/Target/PowerPC/PPC.h @@ -28,7 +28,7 @@ FunctionPass *createPPCBranchSelectionPass(); FunctionPass *createPPCISelDag(PPCTargetMachine &TM); FunctionPass *createPPCAsmPrinterPass(raw_ostream &OS, PPCTargetMachine &TM, - bool Fast, bool Verbose); + unsigned OptLevel, bool Verbose); FunctionPass *createPPCCodeEmitterPass(PPCTargetMachine &TM, MachineCodeEmitter &MCE); } // end namespace llvm; diff --git a/lib/Target/PowerPC/PPCTargetMachine.cpp b/lib/Target/PowerPC/PPCTargetMachine.cpp index 1d3787faa6..3e1dc3253b 100644 --- a/lib/Target/PowerPC/PPCTargetMachine.cpp +++ b/lib/Target/PowerPC/PPCTargetMachine.cpp @@ -129,29 +129,31 @@ PPC64TargetMachine::PPC64TargetMachine(const Module &M, const std::string &FS) // Pass Pipeline Configuration //===----------------------------------------------------------------------===// -bool PPCTargetMachine::addInstSelector(PassManagerBase &PM, bool Fast) { +bool PPCTargetMachine::addInstSelector(PassManagerBase &PM, unsigned OptLevel) { // Install an instruction selector. PM.add(createPPCISelDag(*this)); return false; } -bool PPCTargetMachine::addPreEmitPass(PassManagerBase &PM, bool Fast) { +bool PPCTargetMachine::addPreEmitPass(PassManagerBase &PM, unsigned OptLevel) { // Must run branch selection immediately preceding the asm printer. PM.add(createPPCBranchSelectionPass()); return false; } -bool PPCTargetMachine::addAssemblyEmitter(PassManagerBase &PM, bool Fast, - bool Verbose, raw_ostream &Out) { +bool PPCTargetMachine::addAssemblyEmitter(PassManagerBase &PM, + unsigned OptLevel, + bool Verbose, + raw_ostream &Out) { assert(AsmPrinterCtor && "AsmPrinter was not linked in"); if (AsmPrinterCtor) - PM.add(AsmPrinterCtor(Out, *this, Fast, Verbose)); + PM.add(AsmPrinterCtor(Out, *this, OptLevel, Verbose)); return false; } -bool PPCTargetMachine::addCodeEmitter(PassManagerBase &PM, bool Fast, +bool PPCTargetMachine::addCodeEmitter(PassManagerBase &PM, unsigned OptLevel, bool DumpAsm, MachineCodeEmitter &MCE) { // The JIT should use the static relocation model in ppc32 mode, PIC in ppc64. // FIXME: This should be moved to TargetJITInfo!! @@ -176,20 +178,20 @@ bool PPCTargetMachine::addCodeEmitter(PassManagerBase &PM, bool Fast, if (DumpAsm) { assert(AsmPrinterCtor && "AsmPrinter was not linked in"); if (AsmPrinterCtor) - PM.add(AsmPrinterCtor(errs(), *this, Fast, true)); + PM.add(AsmPrinterCtor(errs(), *this, OptLevel, true)); } return false; } -bool PPCTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM, bool Fast, +bool PPCTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM, unsigned OptLevel, bool DumpAsm, MachineCodeEmitter &MCE) { // Machine code emitter pass for PowerPC. PM.add(createPPCCodeEmitterPass(*this, MCE)); if (DumpAsm) { assert(AsmPrinterCtor && "AsmPrinter was not linked in"); if (AsmPrinterCtor) - PM.add(AsmPrinterCtor(errs(), *this, Fast, true)); + PM.add(AsmPrinterCtor(errs(), *this, OptLevel, true)); } return false; diff --git a/lib/Target/PowerPC/PPCTargetMachine.h b/lib/Target/PowerPC/PPCTargetMachine.h index d33eb79764..2f839fb07b 100644 --- a/lib/Target/PowerPC/PPCTargetMachine.h +++ b/lib/Target/PowerPC/PPCTargetMachine.h @@ -46,7 +46,7 @@ protected: // set this functions to ctor pointer at startup time if they are linked in. typedef FunctionPass *(*AsmPrinterCtorFn)(raw_ostream &o, PPCTargetMachine &tm, - bool fast, bool verbose); + unsigned OptLevel, bool verbose); static AsmPrinterCtorFn AsmPrinterCtor; public: @@ -76,13 +76,13 @@ public: } // Pass Pipeline Configuration - virtual bool addInstSelector(PassManagerBase &PM, bool Fast); - virtual bool addPreEmitPass(PassManagerBase &PM, bool Fast); - virtual bool addAssemblyEmitter(PassManagerBase &PM, bool Fast, + virtual bool addInstSelector(PassManagerBase &PM, unsigned OptLevel); + virtual bool addPreEmitPass(PassManagerBase &PM, unsigned OptLevel); + virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel, bool Verbose, raw_ostream &Out); - virtual bool addCodeEmitter(PassManagerBase &PM, bool Fast, + virtual bool addCodeEmitter(PassManagerBase &PM, unsigned OptLevel, bool DumpAsm, MachineCodeEmitter &MCE); - virtual bool addSimpleCodeEmitter(PassManagerBase &PM, bool Fast, + virtual bool addSimpleCodeEmitter(PassManagerBase &PM, unsigned OptLevel, bool DumpAsm, MachineCodeEmitter &MCE); virtual bool getEnableTailMergeDefault() const; }; diff --git a/lib/Target/Sparc/AsmPrinter/SparcAsmPrinter.cpp b/lib/Target/Sparc/AsmPrinter/SparcAsmPrinter.cpp index ccb0dd9a6c..ab1868425c 100644 --- a/lib/Target/Sparc/AsmPrinter/SparcAsmPrinter.cpp +++ b/lib/Target/Sparc/AsmPrinter/SparcAsmPrinter.cpp @@ -48,9 +48,9 @@ namespace { typedef std::map<const Value *, unsigned> ValueMapTy; ValueMapTy NumberForBB; public: - SparcAsmPrinter(raw_ostream &O, TargetMachine &TM, - const TargetAsmInfo *T, bool F, bool V) - : AsmPrinter(O, TM, T, F, V) {} + explicit SparcAsmPrinter(raw_ostream &O, TargetMachine &TM, + const TargetAsmInfo *T, unsigned OL, bool V) + : AsmPrinter(O, TM, T, OL, V) {} virtual const char *getPassName() const { return "Sparc Assembly Printer"; @@ -82,8 +82,9 @@ namespace { /// FunctionPass *llvm::createSparcCodePrinterPass(raw_ostream &o, TargetMachine &tm, - bool fast, bool verbose) { - return new SparcAsmPrinter(o, tm, tm.getTargetAsmInfo(), fast, verbose); + unsigned OptLevel, + bool verbose) { + return new SparcAsmPrinter(o, tm, tm.getTargetAsmInfo(), OptLevel, verbose); } /// runOnMachineFunction - This uses the printInstruction() diff --git a/lib/Target/Sparc/Sparc.h b/lib/Target/Sparc/Sparc.h index 0a139f6a07..74b2e47614 100644 --- a/lib/Target/Sparc/Sparc.h +++ b/lib/Target/Sparc/Sparc.h @@ -25,7 +25,7 @@ namespace llvm { FunctionPass *createSparcISelDag(SparcTargetMachine &TM); FunctionPass *createSparcCodePrinterPass(raw_ostream &OS, TargetMachine &TM, - bool Fast, bool Verbose); + unsigned OptLevel, bool Verbose); FunctionPass *createSparcDelaySlotFillerPass(TargetMachine &TM); FunctionPass *createSparcFPMoverPass(TargetMachine &TM); } // end namespace llvm; diff --git a/lib/Target/Sparc/SparcTargetMachine.cpp b/lib/Target/Sparc/SparcTargetMachine.cpp index 4ebca3f6bb..cabfce118a 100644 --- a/lib/Target/Sparc/SparcTargetMachine.cpp +++ b/lib/Target/Sparc/SparcTargetMachine.cpp @@ -68,7 +68,8 @@ unsigned SparcTargetMachine::getModuleMatchQuality(const Module &M) { #endif } -bool SparcTargetMachine::addInstSelector(PassManagerBase &PM, bool Fast) { +bool SparcTargetMachine::addInstSelector(PassManagerBase &PM, + unsigned OptLevel) { PM.add(createSparcISelDag(*this)); return false; } @@ -76,15 +77,17 @@ bool SparcTargetMachine::addInstSelector(PassManagerBase &PM, bool Fast) { /// addPreEmitPass - This pass may be implemented by targets that want to run /// passes immediately before machine code is emitted. This should return /// true if -print-machineinstrs should print out the code after the passes. -bool SparcTargetMachine::addPreEmitPass(PassManagerBase &PM, bool Fast) { +bool SparcTargetMachine::addPreEmitPass(PassManagerBase &PM, unsigned OptLevel){ PM.add(createSparcFPMoverPass(*this)); PM.add(createSparcDelaySlotFillerPass(*this)); return true; } -bool SparcTargetMachine::addAssemblyEmitter(PassManagerBase &PM, bool Fast, - bool Verbose, raw_ostream &Out) { +bool SparcTargetMachine::addAssemblyEmitter(PassManagerBase &PM, + unsigned OptLevel, + bool Verbose, + raw_ostream &Out) { // Output assembly language. - PM.add(createSparcCodePrinterPass(Out, *this, Fast, Verbose)); + PM.add(createSparcCodePrinterPass(Out, *this, OptLevel, Verbose)); return false; } diff --git a/lib/Target/Sparc/SparcTargetMachine.h b/lib/Target/Sparc/SparcTargetMachine.h index e775448e45..927cbb5fa1 100644 --- a/lib/Target/Sparc/SparcTargetMachine.h +++ b/lib/Target/Sparc/SparcTargetMachine.h @@ -51,9 +51,9 @@ public: static unsigned getModuleMatchQuality(const Module &M); // Pass Pipeline Configuration - virtual bool addInstSelector(PassManagerBase &PM, bool Fast); - virtual bool addPreEmitPass(PassManagerBase &PM, bool Fast); - virtual bool addAssemblyEmitter(PassManagerBase &PM, bool Fast, + virtual bool addInstSelector(PassManagerBase &PM, unsigned OptLevel); + virtual bool addPreEmitPass(PassManagerBase &PM, unsigned OptLevel); + virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel, bool Verbose, raw_ostream &Out); }; diff --git a/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h b/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h index 65af91ac38..ecb0f4db74 100644 --- a/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h +++ b/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h @@ -33,9 +33,9 @@ class VISIBILITY_HIDDEN X86ATTAsmPrinter : public AsmPrinter { MachineModuleInfo *MMI; const X86Subtarget *Subtarget; public: - X86ATTAsmPrinter(raw_ostream &O, X86TargetMachine &TM, - const TargetAsmInfo *T, bool F, bool V) - : AsmPrinter(O, TM, T, F, V), DW(0), MMI(0) { + explicit X86ATTAsmPrinter(raw_ostream &O, X86TargetMachine &TM, + const TargetAsmInfo *T, unsigned OL, bool V) + : AsmPrinter(O, TM, T, OL, V), DW(0), MMI(0) { Subtarget = &TM.getSubtarget<X86Subtarget>(); } diff --git a/lib/Target/X86/AsmPrinter/X86AsmPrinter.cpp b/lib/Target/X86/AsmPrinter/X86AsmPrinter.cpp index d64aaa6edb..85c5471277 100644 --- a/lib/Target/X86/AsmPrinter/X86AsmPrinter.cpp +++ b/lib/Target/X86/AsmPrinter/X86AsmPrinter.cpp @@ -25,13 +25,15 @@ using namespace llvm; /// FunctionPass *llvm::createX86CodePrinterPass(raw_ostream &o, X86TargetMachine &tm, - bool fast, bool verbose) { + unsigned OptLevel, bool verbose) { const X86Subtarget *Subtarget = &tm.getSubtarget<X86Subtarget>(); if (Subtarget->isFlavorIntel()) { - return new X86IntelAsmPrinter(o, tm, tm.getTargetAsmInfo(), fast, verbose); + return new X86IntelAsmPrinter(o, tm, tm.getTargetAsmInfo(), + OptLevel, verbose); } else { - return new X86ATTAsmPrinter(o, tm, tm.getTargetAsmInfo(), fast, verbose); + return new X86ATTAsmPrinter(o, tm, tm.getTargetAsmInfo(), + OptLevel, verbose); } } diff --git a/lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.h b/lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.h index 489d946790..054cd9c70f 100644 --- a/lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.h +++ b/lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.h @@ -25,9 +25,9 @@ namespace llvm { struct VISIBILITY_HIDDEN X86IntelAsmPrinter : public AsmPrinter { - X86IntelAsmPrinter(raw_ostream &O, X86TargetMachine &TM, - const TargetAsmInfo *T, bool F, bool V) - : AsmPrinter(O, TM, T, F, V) {} + explicit X86IntelAsmPrinter(raw_ostream &O, X86TargetMachine &TM, + const TargetAsmInfo *T, unsigned OL, bool V) + : AsmPrinter(O, TM, T, OL, V) {} virtual const char *getPassName() const { return "X86 Intel-Style Assembly Printer"; diff --git a/lib/Target/X86/X86.h b/lib/Target/X86/X86.h index 72ff02ba6f..9dad017dd3 100644 --- a/lib/Target/X86/X86.h +++ b/lib/Target/X86/X86.h @@ -25,7 +25,7 @@ class raw_ostream; /// createX86ISelDag - This pass converts a legalized DAG into a /// X86-specific DAG, ready for instruction scheduling. /// -FunctionPass *createX86ISelDag(X86TargetMachine &TM, bool Fast); +FunctionPass *createX86ISelDag(X86TargetMachine &TM, unsigned OptSize); /// createX86FloatingPointStackifierPass - This function returns a pass which /// converts floating point register references and pseudo instructions into @@ -44,7 +44,7 @@ FunctionPass *createX87FPRegKillInserterPass(); /// FunctionPass *createX86CodePrinterPass(raw_ostream &o, X86TargetMachine &tm, - bool fast, bool Verbose); + unsigned OptLevel, bool Verbose); /// createX86CodeEmitterPass - Return a pass that emits the collected X86 code /// to the specified MCE object. diff --git a/lib/Target/X86/X86ISelDAGToDAG.cpp b/lib/Target/X86/X86ISelDAGToDAG.cpp index 4b698cec1a..7da43e97dc 100644 --- a/lib/Target/X86/X86ISelDAGToDAG.cpp +++ b/lib/Target/X86/X86ISelDAGToDAG.cpp @@ -134,8 +134,8 @@ namespace { bool OptForSize; public: - X86DAGToDAGISel(X86TargetMachine &tm, bool fast) - : SelectionDAGISel(tm, fast), + explicit X86DAGToDAGISel(X86TargetMachine &tm, unsigned OptLevel) + : SelectionDAGISel(tm, OptLevel), TM(tm), X86Lowering(*TM.getTargetLowering()), Subtarget(&TM.getSubtarget<X86Subtarget>()), OptForSize(false) {} @@ -306,7 +306,7 @@ static inline bool isNonImmUse(SDNode *Root, SDNode *Def, SDNode *ImmedUse) { bool X86DAGToDAGISel::IsLegalAndProfitableToFold(SDNode *N, SDNode *U, SDNode *Root) const { - if (Fast) return false; + if (OptLevel == 0) return false; if (U == Root) switch (U->getOpcode()) { @@ -512,7 +512,7 @@ static bool isCalleeLoad(SDValue Callee, SDValue &Chain) { /// PreprocessForRMW - Preprocess the DAG to make instruction selection better. -/// This is only run if not in -fast mode (aka -O0). +/// This is only run if not in -O0 mode. /// This allows the instruction selector to pick more read-modify-write /// instructions. This is a common case: /// @@ -714,10 +714,10 @@ void X86DAGToDAGISel::InstructionSelect() { OptForSize = F->hasFnAttr(Attribute::OptimizeForSize); DEBUG(BB->dump()); - if (!Fast) + if (OptLevel != 0) PreprocessForRMW(); - // FIXME: This should only happen when not -fast. + // FIXME: This should only happen when not compiled with -O0. PreprocessForFPConvert(); // Codegen the basic block. @@ -1744,6 +1744,6 @@ SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode, /// createX86ISelDag - This pass converts a legalized DAG into a /// X86-specific DAG, ready for instruction scheduling. /// -FunctionPass *llvm::createX86ISelDag(X86TargetMachine &TM, bool Fast) { - return new X86DAGToDAGISel(TM, Fast); +FunctionPass *llvm::createX86ISelDag(X86TargetMachine &TM, unsigned OptLevel) { + return new X86DAGToDAGISel(TM, OptLevel); } diff --git a/lib/Target/X86/X86TargetMachine.cpp b/lib/Target/X86/X86TargetMachine.cpp index a20e1c4489..df086e8cea 100644 --- a/lib/Target/X86/X86TargetMachine.cpp +++ b/lib/Target/X86/X86TargetMachine.cpp @@ -180,9 +180,9 @@ X86TargetMachine::X86TargetMachine(const Module &M, const std::string &FS, // Pass Pipeline Configuration //===----------------------------------------------------------------------===// -bool X86TargetMachine::addInstSelector(PassManagerBase &PM, bool Fast) { +bool X86TargetMachine::addInstSelector(PassManagerBase &PM, unsigned OptLevel) { // Install an instruction selector. - PM.add(createX86ISelDag(*this, Fast)); + PM.add(createX86ISelDag(*this, OptLevel)); // If we're using Fast-ISel, clean up the mess. if (EnableFastISel) @@ -194,27 +194,29 @@ bool X86TargetMachine::addInstSelector(PassManagerBase &PM, bool Fast) { return false; } -bool X86TargetMachine::addPreRegAlloc(PassManagerBase &PM, bool Fast) { +bool X86TargetMachine::addPreRegAlloc(PassManagerBase &PM, unsigned OptLevel) { // Calculate and set max stack object alignment early, so we can decide // whether we will need stack realignment (and thus FP). PM.add(createX86MaxStackAlignmentCalculatorPass()); return false; // -print-machineinstr shouldn't print after this. } -bool X86TargetMachine::addPostRegAlloc(PassManagerBase &PM, bool Fast) { +bool X86TargetMachine::addPostRegAlloc(PassManagerBase &PM, unsigned OptLevel) { PM.add(createX86FloatingPointStackifierPass()); return true; // -print-machineinstr should print after this. } -bool X86TargetMachine::addAssemblyEmitter(PassManagerBase &PM, bool Fast, - bool Verbose, raw_ostream &Out) { +bool X86TargetMachine::addAssemblyEmitter(PassManagerBase &PM, + unsigned OptLevel, + bool Verbose, + raw_ostream &Out) { assert(AsmPrinterCtor && "AsmPrinter was not linked in"); if (AsmPrinterCtor) - PM.add(AsmPrinterCtor(Out, *this, Fast, Verbose)); + PM.add(AsmPrinterCtor(Out, *this, OptLevel, Verbose)); return false; } -bool X86TargetMachine::addCodeEmitter(PassManagerBase &PM, bool Fast, +bool X86TargetMachine::addCodeEmitter(PassManagerBase &PM, unsigned OptLevel, bool DumpAsm, MachineCodeEmitter &MCE) { // FIXME: Move this to TargetJITInfo! // On Darwin, do not override 64-bit setting made in X86TargetMachine(). @@ -236,19 +238,20 @@ bool X86TargetMachine::addCodeEmitter(PassManagerBase &PM, bool Fast, if (DumpAsm) { assert(AsmPrinterCtor && "AsmPrinter was not linked in"); if (AsmPrinterCtor) - PM.add(AsmPrinterCtor(errs(), *this, Fast, true)); + PM.add(AsmPrinterCtor(errs(), *this, OptLevel, true)); } return false; } -bool X86TargetMachine::addSimpleCodeEmitter(PassManagerBase &PM, bool Fast, - bool DumpAsm, MachineCodeEmitter &MCE) { +bool X86TargetMachine::addSimpleCodeEmitter(PassManagerBase &PM, + unsigned OptLevel, bool DumpAsm, + MachineCodeEmitter &MCE) { PM.add(createX86CodeEmitterPass(*this, MCE)); if (DumpAsm) { assert(AsmPrinterCtor && "AsmPrinter was not linked in"); if (AsmPrinterCtor) - PM.add(AsmPrinterCtor(errs(), *this, Fast, true)); + PM.add(AsmPrinterCtor(errs(), *this, OptLevel, true)); } return false; diff --git a/lib/Target/X86/X86TargetMachine.h b/lib/Target/X86/X86TargetMachine.h index fdc00fa1ef..4b4e26f600 100644 --- a/lib/Target/X86/X86TargetMachine.h +++ b/lib/Target/X86/X86TargetMachine.h @@ -45,7 +45,7 @@ protected: // set this functions to ctor pointer at startup time if they are linked in. typedef FunctionPass *(*AsmPrinterCtorFn)(raw_ostream &o, X86TargetMachine &tm, - bool fast, bool verbose); + unsigned OptLevel, bool verbose); static AsmPrinterCtorFn AsmPrinterCtor; public: @@ -74,14 +74,14 @@ public: } // Set up the pass pipeline. - virtual bool addInstSelector(PassManagerBase &PM, bool Fast); - virtual bool addPreRegAlloc(PassManagerBase &PM, bool Fast); - virtual bool addPostRegAlloc(PassManagerBase &PM, bool Fast); - virtual bool addAssemblyEmitter(PassManagerBase &PM, bool Fast, + virtual bool addInstSelector(PassManagerBase &PM, unsigned OptLevel); + virtual bool addPreRegAlloc(PassManagerBase &PM, unsigned OptLevel); + virtual bool addPostRegAlloc(PassManagerBase &PM, unsigned OptLevel); + virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel, bool Verbose, raw_ostream &Out); - virtual bool addCodeEmitter(PassManagerBase &PM, bool Fast, + virtual bool addCodeEmitter(PassManagerBase &PM, unsigned OptLevel, bool DumpAsm, MachineCodeEmitter &MCE); - virtual bool addSimpleCodeEmitter(PassManagerBase &PM, bool Fast, + virtual bool addSimpleCodeEmitter(PassManagerBase &PM, unsigned OptLevel, bool DumpAsm, MachineCodeEmitter &MCE); /// symbolicAddressesAreRIPRel - Return true if symbolic addresses are diff --git a/lib/Target/XCore/XCore.h b/lib/Target/XCore/XCore.h index 62cf4032d6..1c99d887b0 100644 --- a/lib/Target/XCore/XCore.h +++ b/lib/Target/XCore/XCore.h @@ -24,7 +24,7 @@ namespace llvm { FunctionPass *createXCoreISelDag(XCoreTargetMachine &TM); FunctionPass *createXCoreCodePrinterPass(raw_ostream &OS, XCoreTargetMachine &TM, - bool Fast, bool Verbose); + unsigned OptLevel, bool Verbose); } // end namespace llvm; // Defines symbolic names for XCore registers. This defines a mapping from diff --git a/lib/Target/XCore/XCoreAsmPrinter.cpp b/lib/Target/XCore/XCoreAsmPrinter.cpp index a3907e9fe6..accc35afbe 100644 --- a/lib/Target/XCore/XCoreAsmPrinter.cpp +++ b/lib/Target/XCore/XCoreAsmPrinter.cpp @@ -58,8 +58,8 @@ namespace { const XCoreSubtarget &Subtarget; public: XCoreAsmPrinter(raw_ostream &O, XCoreTargetMachine &TM, - const TargetAsmInfo *T, bool F, bool V) - : AsmPrinter(O, TM, T, F, V), DW(0), + const TargetAsmInfo *T, unsigned OL, bool V) + : AsmPrinter(O, TM, T, OL, V), DW(0), Subtarget(*TM.getSubtargetImpl()) {} virtual const char *getPassName() const { @@ -105,8 +105,9 @@ namespace { /// FunctionPass *llvm::createXCoreCodePrinterPass(raw_ostream &o, XCoreTargetMachine &tm, - bool fast, bool verbose) { - return new XCoreAsmPrinter(o, tm, tm.getTargetAsmInfo(), fast, verbose); + unsigned OptLevel, + bool verbose) { + return new XCoreAsmPrinter(o, tm, tm.getTargetAsmInfo(), OptLevel, verbose); } // PrintEscapedString - Print each character of the specified string, escaping diff --git a/lib/Target/XCore/XCoreTargetMachine.cpp b/lib/Target/XCore/XCoreTargetMachine.cpp index 1bfd7af1de..bb0ba775a2 100644 --- a/lib/Target/XCore/XCoreTargetMachine.cpp +++ b/lib/Target/XCore/XCoreTargetMachine.cpp @@ -55,14 +55,17 @@ unsigned XCoreTargetMachine::getModuleMatchQuality(const Module &M) { return 0; } -bool XCoreTargetMachine::addInstSelector(PassManagerBase &PM, bool Fast) { +bool XCoreTargetMachine::addInstSelector(PassManagerBase &PM, + unsigned OptLevel) { PM.add(createXCoreISelDag(*this)); return false; } -bool XCoreTargetMachine::addAssemblyEmitter(PassManagerBase &PM, bool Fast, - bool Verbose, raw_ostream &Out) { +bool XCoreTargetMachine::addAssemblyEmitter(PassManagerBase &PM, + unsigned OptLevel, + bool Verbose, + raw_ostream &Out) { // Output assembly language. - PM.add(createXCoreCodePrinterPass(Out, *this, Fast, Verbose)); + PM.add(createXCoreCodePrinterPass(Out, *this, OptLevel, Verbose)); return false; } diff --git a/lib/Target/XCore/XCoreTargetMachine.h b/lib/Target/XCore/XCoreTargetMachine.h index 081bdbdaf2..e57e672fad 100644 --- a/lib/Target/XCore/XCoreTargetMachine.h +++ b/lib/Target/XCore/XCoreTargetMachine.h @@ -52,8 +52,8 @@ public: static unsigned getModuleMatchQuality(const Module &M); // Pass Pipeline Configuration - virtual bool addInstSelector(PassManagerBase &PM, bool Fast); - virtual bool addAssemblyEmitter(PassManagerBase &PM, bool Fast, + virtual bool addInstSelector(PassManagerBase &PM, unsigned OptLevel); + virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel, bool Verbose, raw_ostream &Out); }; diff --git a/test/CodeGen/Generic/2006-06-12-LowerSwitchCrash.ll b/test/CodeGen/Generic/2006-06-12-LowerSwitchCrash.ll index 47ee7c5fcc..b644bd2be7 100644 --- a/test/CodeGen/Generic/2006-06-12-LowerSwitchCrash.ll +++ b/test/CodeGen/Generic/2006-06-12-LowerSwitchCrash.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -fast +; RUN: llvm-as < %s | llc -O0 define float @test(i32 %tmp12771278) { switch i32 %tmp12771278, label %bb1279 [ diff --git a/test/CodeGen/Generic/2006-06-13-ComputeMaskedBitsCrash.ll b/test/CodeGen/Generic/2006-06-13-ComputeMaskedBitsCrash.ll index 920cf3c464..1aa3c62f95 100644 --- a/test/CodeGen/Generic/2006-06-13-ComputeMaskedBitsCrash.ll +++ b/test/CodeGen/Generic/2006-06-13-ComputeMaskedBitsCrash.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -fast +; RUN: llvm-as < %s | llc -O0 %struct.cl_perfunc_opts = type { i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i32, i32, i32, i32, i32, i32, i32 } @cl_pf_opts = external global %struct.cl_perfunc_opts ; <%struct.cl_perfunc_opts*> [#uses=2] diff --git a/test/CodeGen/Generic/2007-04-13-SwitchLowerBadPhi.ll b/test/CodeGen/Generic/2007-04-13-SwitchLowerBadPhi.ll index b95a361390..1418bbf16d 100644 --- a/test/CodeGen/Generic/2007-04-13-SwitchLowerBadPhi.ll +++ b/test/CodeGen/Generic/2007-04-13-SwitchLowerBadPhi.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -fast +; RUN: llvm-as < %s | llc -O0 ; PR 1323 ; ModuleID = 'test.bc' diff --git a/test/CodeGen/PowerPC/cr_spilling.ll b/test/CodeGen/PowerPC/cr_spilling.ll index 87315e0342..4584c71182 100644 --- a/test/CodeGen/PowerPC/cr_spilling.ll +++ b/test/CodeGen/PowerPC/cr_spilling.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -march=ppc32 -regalloc=local -fast -relocation-model=pic -o - +; RUN: llvm-as < %s | llc -march=ppc32 -regalloc=local -O0 -relocation-model=pic -o - ; PR1638 @.str242 = external constant [3 x i8] ; <[3 x i8]*> [#uses=1] diff --git a/test/CodeGen/X86/2008-04-15-LiveVariableBug.ll b/test/CodeGen/X86/2008-04-15-LiveVariableBug.ll index 8cdff563a3..4bb8c6d27a 100644 --- a/test/CodeGen/X86/2008-04-15-LiveVariableBug.ll +++ b/test/CodeGen/X86/2008-04-15-LiveVariableBug.ll @@ -1,5 +1,5 @@ ; RUN: llvm-as < %s | llc -mtriple=x86_64-apple-darwin -; RUN: llvm-as < %s | llc -mtriple=x86_64-apple-darwin -relocation-model=pic -disable-fp-elim -fast -regalloc=local +; RUN: llvm-as < %s | llc -mtriple=x86_64-apple-darwin -relocation-model=pic -disable-fp-elim -O0 -regalloc=local %struct.CGPoint = type { double, double } %struct.NSArray = type { %struct.NSObject } diff --git a/test/CodeGen/X86/2008-05-21-CoalescerBug.ll b/test/CodeGen/X86/2008-05-21-CoalescerBug.ll index bed218fb70..9ecd5814de 100644 --- a/test/CodeGen/X86/2008-05-21-CoalescerBug.ll +++ b/test/CodeGen/X86/2008-05-21-CoalescerBug.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -march=x86 -fast -fast-isel=false | grep mov | count 5 +; RUN: llvm-as < %s | llc -march=x86 -O0 -fast-isel=false | grep mov | count 5 ; PR2343 %llvm.dbg.anchor.type = type { i32, i32 } diff --git a/test/CodeGen/X86/2009-03-23-LinearScanBug.ll b/test/CodeGen/X86/2009-03-23-LinearScanBug.ll index 0a4501e73a..b5298aee30 100644 --- a/test/CodeGen/X86/2009-03-23-LinearScanBug.ll +++ b/test/CodeGen/X86/2009-03-23-LinearScanBug.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -mtriple=i386-apple-darwin -fast +; RUN: llvm-as < %s | llc -mtriple=i386-apple-darwin -O0 define fastcc void @optimize_bit_field() nounwind { bb4: diff --git a/test/CodeGen/X86/2009-04-14-IllegalRegs.ll b/test/CodeGen/X86/2009-04-14-IllegalRegs.ll index 5dda4e9ec0..0d66f6984f 100644 --- a/test/CodeGen/X86/2009-04-14-IllegalRegs.ll +++ b/test/CodeGen/X86/2009-04-14-IllegalRegs.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -mtriple=i386-apple-darwin -fast -regalloc=local | not grep sil +; RUN: llvm-as < %s | llc -mtriple=i386-apple-darwin -O0 -regalloc=local | not grep sil ; rdar://6787136 %struct.X = type { i8, [32 x i8] } diff --git a/test/CodeGen/X86/add-with-overflow.ll b/test/CodeGen/X86/add-with-overflow.ll index bfb86fd9e6..d015cebbbd 100644 --- a/test/CodeGen/X86/add-with-overflow.ll +++ b/test/CodeGen/X86/add-with-overflow.ll @@ -1,7 +1,7 @@ ; RUN: llvm-as < %s | llc -march=x86 | grep {jo} | count 2 ; RUN: llvm-as < %s | llc -march=x86 | grep {jb} | count 2 -; RUN: llvm-as < %s | llc -march=x86 -fast | grep {jo} | count 2 -; RUN: llvm-as < %s | llc -march=x86 -fast | grep {jb} | count 2 +; RUN: llvm-as < %s | llc -march=x86 -O0 | grep {jo} | count 2 +; RUN: llvm-as < %s | llc -march=x86 -O0 | grep {jb} | count 2 @ok = internal constant [4 x i8] c"%d\0A\00" @no = internal constant [4 x i8] c"no\0A\00" diff --git a/test/CodeGen/X86/fast-isel-bail.ll b/test/CodeGen/X86/fast-isel-bail.ll index fa65d209b2..fb4f37ef90 100644 --- a/test/CodeGen/X86/fast-isel-bail.ll +++ b/test/CodeGen/X86/fast-isel-bail.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -march=x86 -fast +; RUN: llvm-as < %s | llc -march=x86 -O0 ; This file is for regression tests for cases where FastISel needs ; to gracefully bail out and let SelectionDAGISel take over. diff --git a/test/CodeGen/X86/fast-isel-gep-sext.ll b/test/CodeGen/X86/fast-isel-gep-sext.ll index ec420ff026..4e988f5e5a 100644 --- a/test/CodeGen/X86/fast-isel-gep-sext.ll +++ b/test/CodeGen/X86/fast-isel-gep-sext.ll @@ -1,5 +1,5 @@ -; RUN: llvm-as < %s | llc -march=x86-64 -fast | grep movslq -; RUN: llvm-as < %s | llc -march=x86 -fast +; RUN: llvm-as < %s | llc -march=x86-64 -O0 | grep movslq +; RUN: llvm-as < %s | llc -march=x86 -O0 ; PR3181 ; GEP indices are interpreted as signed integers, so they diff --git a/test/CodeGen/X86/fast-isel-shift-imm.ll b/test/CodeGen/X86/fast-isel-shift-imm.ll index c47b99013a..7d8c9f5e00 100644 --- a/test/CodeGen/X86/fast-isel-shift-imm.ll +++ b/test/CodeGen/X86/fast-isel-shift-imm.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -march=x86 -fast | grep {sarl \$80, %eax} +; RUN: llvm-as < %s | llc -march=x86 -O0 | grep {sarl \$80, %eax} ; PR3242 define i32 @foo(i32 %x) nounwind { diff --git a/test/CodeGen/X86/pr1489.ll b/test/CodeGen/X86/pr1489.ll index a7f3e795c6..10fa96a3b8 100644 --- a/test/CodeGen/X86/pr1489.ll +++ b/test/CodeGen/X86/pr1489.ll @@ -1,5 +1,5 @@ -; RUN: llvm-as < %s | llc -disable-fp-elim -fast -mcpu=i486 | grep 1082126238 | count 3 -; RUN: llvm-as < %s | llc -disable-fp-elim -fast -mcpu=i486 | grep 3058016715 | count 1 +; RUN: llvm-as < %s | llc -disable-fp-elim -O0 -mcpu=i486 | grep 1082126238 | count 3 +; RUN: llvm-as < %s | llc -disable-fp-elim -O0 -mcpu=i486 | grep 3058016715 | count 1 ;; magic constants are 3.999f and half of 3.999 ; ModuleID = '1489.c' target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64" diff --git a/test/CodeGen/X86/volatile.ll b/test/CodeGen/X86/volatile.ll index e40f87b30e..f919b5de49 100644 --- a/test/CodeGen/X86/volatile.ll +++ b/test/CodeGen/X86/volatile.ll @@ -1,5 +1,5 @@ ; RUN: llvm-as < %s | llc -march=x86 -mattr=sse2 | grep movsd | count 5 -; RUN: llvm-as < %s | llc -march=x86 -mattr=sse2 -fast | grep movsd | count 5 +; RUN: llvm-as < %s | llc -march=x86 -mattr=sse2 -O0 | grep movsd | count 5 @x = external global double diff --git a/test/DebugInfo/2008-11-05-InlinedFuncStart.ll b/test/DebugInfo/2008-11-05-InlinedFuncStart.ll index a35a88ebd6..c494190b4e 100644 --- a/test/DebugInfo/2008-11-05-InlinedFuncStart.ll +++ b/test/DebugInfo/2008-11-05-InlinedFuncStart.ll @@ -1,5 +1,5 @@ ; RUN: llvm-as < %s | llc -; RUN: llvm-as < %s | llc -fast +; RUN: llvm-as < %s | llc -O0 %llvm.dbg.anchor.type = type { i32, i32 } %llvm.dbg.basictype.type = type { i32, { }*, i8*, { }*, i32, i64, i64, i64, i32, i32 } %llvm.dbg.compile_unit.type = type { i32, { }*, i32, i8*, i8*, i8* } diff --git a/test/DebugInfo/2009-01-30-Method.ll b/test/DebugInfo/2009-01-30-Method.ll index c17dca1a92..d49076cf31 100644 --- a/test/DebugInfo/2009-01-30-Method.ll +++ b/test/DebugInfo/2009-01-30-Method.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -fast | grep "\\"foo" | count 3 +; RUN: llvm-as < %s | llc -O0 | grep "\\"foo" | count 3 ; 1 declaration, 1 definition and 1 pubnames entry. target triple = "i386-apple-darwin*" %llvm.dbg.anchor.type = type { i32, i32 } diff --git a/test/DebugInfo/deaddebuglabel.ll b/test/DebugInfo/deaddebuglabel.ll index 5efa27a418..edab7e84be 100644 --- a/test/DebugInfo/deaddebuglabel.ll +++ b/test/DebugInfo/deaddebuglabel.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -fast | grep "label" | count 8 +; RUN: llvm-as < %s | llc -O0 | grep "label" | count 8 ; PR2614 ; XFAIL: * diff --git a/test/DebugInfo/forwardDecl.ll b/test/DebugInfo/forwardDecl.ll index f3e95dd588..a3d1927bdb 100644 --- a/test/DebugInfo/forwardDecl.ll +++ b/test/DebugInfo/forwardDecl.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -fast | %prcontext ST 1 | grep 0x1 | count 1 +; RUN: llvm-as < %s | llc -O0 | %prcontext ST 1 | grep 0x1 | count 1 target triple = "i386-apple-darwin9.6" %llvm.dbg.anchor.type = type { i32, i32 } diff --git a/test/FrontendC++/2006-11-06-StackTrace.cpp b/test/FrontendC++/2006-11-06-StackTrace.cpp index 15c88df0d1..f6a4428e4c 100644 --- a/test/FrontendC++/2006-11-06-StackTrace.cpp +++ b/test/FrontendC++/2006-11-06-StackTrace.cpp @@ -1,7 +1,7 @@ // This is a regression test on debug info to make sure that we can get a // meaningful stack trace from a C++ program. // RUN: %llvmgcc -S -O0 -g %s -o - | llvm-as | \ -// RUN: llc --disable-fp-elim -o %t.s -f -fast -relocation-model=pic +// RUN: llc --disable-fp-elim -o %t.s -f -O0 -relocation-model=pic // RUN: %compile_c %t.s -o %t.o // RUN: %link %t.o -o %t.exe // RUN: echo {break DeepStack::deepest\nrun 17\nwhere\n} > %t.in diff --git a/test/FrontendC++/2006-11-30-Pubnames.cpp b/test/FrontendC++/2006-11-30-Pubnames.cpp index b53d6aa734..8102713c39 100644 --- a/test/FrontendC++/2006-11-30-Pubnames.cpp +++ b/test/FrontendC++/2006-11-30-Pubnames.cpp @@ -1,7 +1,7 @@ // This is a regression test on debug info to make sure that we can access // qualified global names. // RUN: %llvmgcc -S -O0 -g %s -o - | llvm-as | \ -// RUN: llc --disable-fp-elim -o %t.s -f -fast +// RUN: llc --disable-fp-elim -o %t.s -f -O0 // RUN: %compile_c %t.s -o %t.o // RUN: %link %t.o -o %t.exe // RUN: %llvmdsymutil %t.exe diff --git a/test/FrontendC++/2009-04-21-DtorNames-dbg.cpp b/test/FrontendC++/2009-04-21-DtorNames-dbg.cpp index 4bd8e771e5..dfc607e654 100644 --- a/test/FrontendC++/2009-04-21-DtorNames-dbg.cpp +++ b/test/FrontendC++/2009-04-21-DtorNames-dbg.cpp @@ -1,4 +1,4 @@ -// RUN: %llvmgcc -c -g %s -o - | llc -fast -f -o %t.s +// RUN: %llvmgcc -c -g %s -o - | llc -O0 -f -o %t.s // RUN: %compile_c %t.s -o %t.o // PR4025 diff --git a/tools/llc/llc.cpp b/tools/llc/llc.cpp index 1b84d4d5b1..eff32270e7 100644 --- a/tools/llc/llc.cpp +++ b/tools/llc/llc.cpp @@ -55,8 +55,13 @@ OutputFilename("o", cl::desc("Output filename"), cl::value_desc("filename")); static cl::opt<bool> Force("f", cl::desc("Overwrite output files")); -static cl::opt<bool> Fast("fast", - cl::desc("Generate code quickly, potentially sacrificing code quality")); +// Determine optimization level. Level -O0 is equivalent to "fast" code gen. +static cl::opt<unsigned> +OptLevel("O", + cl::desc("Optimization level. Similar to llvm-gcc -O. (default: -O3)"), + cl::Prefix, + cl::ZeroOrMore, + cl::init(3)); static cl::opt<std::string> TargetTriple("mtriple", cl::desc("Override target triple for module")); @@ -257,7 +262,7 @@ int main(int argc, char **argv) { PM.add(createVerifierPass()); // Ask the target to add backend passes as necessary. - if (Target.addPassesToEmitWholeFile(PM, *Out, FileType, Fast)) { + if (Target.addPassesToEmitWholeFile(PM, *Out, FileType, OptLevel)) { std::cerr << argv[0] << ": target does not support generation of this" << " file type!\n"; if (Out != &outs()) delete Out; @@ -283,7 +288,7 @@ int main(int argc, char **argv) { // Override default to generate verbose assembly. Target.setAsmVerbosityDefault(true); - switch (Target.addPassesToEmitFile(Passes, *Out, FileType, Fast)) { + switch (Target.addPassesToEmitFile(Passes, *Out, FileType, OptLevel)) { default: assert(0 && "Invalid file model!"); return 1; @@ -304,7 +309,7 @@ int main(int argc, char **argv) { break; } - if (Target.addPassesToEmitFileFinish(Passes, MCE, Fast)) { + if (Target.addPassesToEmitFileFinish(Passes, MCE, OptLevel)) { std::cerr << argv[0] << ": target does not support generation of this" << " file type!\n"; if (Out != &outs()) delete Out; diff --git a/utils/TableGen/AsmWriterEmitter.cpp b/utils/TableGen/AsmWriterEmitter.cpp index 93ef6c86a6..6bcc52af8a 100644 --- a/utils/TableGen/AsmWriterEmitter.cpp +++ b/utils/TableGen/AsmWriterEmitter.cpp @@ -650,7 +650,7 @@ void AsmWriterEmitter::run(std::ostream &O) { O << "\";\n\n"; O << " if (TAI->doesSupportDebugInformation() &&\n" - << " DW->ShouldEmitDwarfDebug() && !Fast) {\n" + << " DW->ShouldEmitDwarfDebug() && OptLevel != 0) {\n" << " DebugLoc CurDL = MI->getDebugLoc();\n\n" << " if (!CurDL.isUnknown()) {\n" << " static DebugLocTuple PrevDLT(~0U, ~0U, ~0U);\n" diff --git a/utils/TableGen/DAGISelEmitter.cpp b/utils/TableGen/DAGISelEmitter.cpp index 3335d00f72..b5d334c40d 100644 --- a/utils/TableGen/DAGISelEmitter.cpp +++ b/utils/TableGen/DAGISelEmitter.cpp @@ -465,7 +465,7 @@ public: NumInputRootOps = N->getNumChildren(); if (DisablePatternForFastISel(N, CGP)) - emitCheck("!Fast"); + emitCheck("OptLevel != 0"); emitCheck(PredicateCheck); } |