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authorEvan Cheng <evan.cheng@apple.com>2006-05-17 21:20:27 +0000
committerEvan Cheng <evan.cheng@apple.com>2006-05-17 21:20:27 +0000
commitc01d497255f0d344163178c5f827e8b73f6f04d6 (patch)
tree26c44c94b0d11b61699e7a9e730a8742c4938762
parented96fe8c79b36a38bd9280438656ee539276fb41 (diff)
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Remove PointerType from class Target
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28368 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r--lib/Target/ARM/ARM.td3
-rw-r--r--lib/Target/Alpha/Alpha.td3
-rw-r--r--lib/Target/IA64/IA64.td4
-rw-r--r--lib/Target/PowerPC/PPC.td3
-rw-r--r--lib/Target/Sparc/Sparc.td3
-rw-r--r--lib/Target/Target.td4
-rw-r--r--lib/Target/X86/X86.td3
7 files changed, 0 insertions, 23 deletions
diff --git a/lib/Target/ARM/ARM.td b/lib/Target/ARM/ARM.td
index a7b7e6ed60..3b5b198d71 100644
--- a/lib/Target/ARM/ARM.td
+++ b/lib/Target/ARM/ARM.td
@@ -40,9 +40,6 @@ def ARMInstrInfo : InstrInfo {
//===----------------------------------------------------------------------===//
def ARM : Target {
- // Pointers are 32-bits in size.
- let PointerType = i32;
-
// FIXME: Specify callee-saved registers
let CalleeSavedRegisters = [];
diff --git a/lib/Target/Alpha/Alpha.td b/lib/Target/Alpha/Alpha.td
index 80f03fbe86..c6bba45035 100644
--- a/lib/Target/Alpha/Alpha.td
+++ b/lib/Target/Alpha/Alpha.td
@@ -65,9 +65,6 @@ def : Processor<"ev67" , Alpha21264Itineraries, [FeatureFIX, FeatureCIX]>;
def Alpha : Target {
- // Pointers on Alpha are 64-bits in size.
- let PointerType = i64;
-
let CalleeSavedRegisters =
//saved regs
[R9, R10, R11, R12, R13, R14,
diff --git a/lib/Target/IA64/IA64.td b/lib/Target/IA64/IA64.td
index 30337625c5..aceb30ba2e 100644
--- a/lib/Target/IA64/IA64.td
+++ b/lib/Target/IA64/IA64.td
@@ -91,10 +91,6 @@ def IA64 : Target {
*/
];
- // We don't go anywhere near the LP32 variant of IA64 as
- // sometimes seen in (for example) HP-UX
- let PointerType = i64;
-
// Our instruction set
let InstructionSet = IA64InstrInfo;
diff --git a/lib/Target/PowerPC/PPC.td b/lib/Target/PowerPC/PPC.td
index 10b9095d7d..702b5a31d9 100644
--- a/lib/Target/PowerPC/PPC.td
+++ b/lib/Target/PowerPC/PPC.td
@@ -81,9 +81,6 @@ def PPCInstrInfo : InstrInfo {
def PPC : Target {
- // Pointers on PPC are 32-bits in size.
- let PointerType = i32;
-
// Information about the instructions.
let InstructionSet = PPCInstrInfo;
diff --git a/lib/Target/Sparc/Sparc.td b/lib/Target/Sparc/Sparc.td
index aa8b9e2c72..38b03a4c0d 100644
--- a/lib/Target/Sparc/Sparc.td
+++ b/lib/Target/Sparc/Sparc.td
@@ -75,9 +75,6 @@ def : Proc<"ultrasparc3-vis", [FeatureV9, FeatureV8Deprecated, FeatureVIS]>;
//===----------------------------------------------------------------------===//
def Sparc : Target {
- // Pointers are 32-bits in size.
- let PointerType = i32;
-
// FIXME: Specify callee-saved registers
let CalleeSavedRegisters = [];
diff --git a/lib/Target/Target.td b/lib/Target/Target.td
index 8fbc58e223..36082db0f4 100644
--- a/lib/Target/Target.td
+++ b/lib/Target/Target.td
@@ -271,10 +271,6 @@ class Target {
// saved registers for a target.
list<Register> CalleeSavedRegisters = [];
- // PointerType - Specify the value type to be used to represent pointers in
- // this target. Typically this is an i32 or i64 type.
- ValueType PointerType;
-
// InstructionSet - Instruction set description for this target.
InstrInfo InstructionSet;
diff --git a/lib/Target/X86/X86.td b/lib/Target/X86/X86.td
index aaacc7e671..170ec1302c 100644
--- a/lib/Target/X86/X86.td
+++ b/lib/Target/X86/X86.td
@@ -133,9 +133,6 @@ def X86 : Target {
// Specify the callee saved registers.
let CalleeSavedRegisters = [ESI, EDI, EBX, EBP];
- // Yes, pointers are 32-bits in size.
- let PointerType = i32;
-
// Information about the instructions...
let InstructionSet = X86InstrInfo;