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author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2013-11-18 20:09:47 +0000 |
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committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2013-11-18 20:09:47 +0000 |
commit | e64a2896094be370f5ca3d755f62c762fb94b37a (patch) | |
tree | 380c065a1d26e1dd8a02a6d1a49df1651626752a | |
parent | 15703e0a71e7583b107499045374c364976452e2 (diff) | |
download | llvm-e64a2896094be370f5ca3d755f62c762fb94b37a.tar.gz llvm-e64a2896094be370f5ca3d755f62c762fb94b37a.tar.bz2 llvm-e64a2896094be370f5ca3d755f62c762fb94b37a.tar.xz |
R600/SI: Implement add i64, but do not yet enable.
Test doesn't actually check the output. I need
to fix add i64 being matched for the addressing
calculations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195040 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r-- | lib/Target/R600/SIISelLowering.cpp | 28 | ||||
-rw-r--r-- | lib/Target/R600/SIISelLowering.h | 1 | ||||
-rw-r--r-- | test/CodeGen/R600/add_i64.ll | 45 |
3 files changed, 74 insertions, 0 deletions
diff --git a/lib/Target/R600/SIISelLowering.cpp b/lib/Target/R600/SIISelLowering.cpp index 95b3be7b8f..9435e9b4fc 100644 --- a/lib/Target/R600/SIISelLowering.cpp +++ b/lib/Target/R600/SIISelLowering.cpp @@ -424,6 +424,7 @@ SDValue SITargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>(); switch (Op.getOpcode()) { default: return AMDGPUTargetLowering::LowerOperation(Op, DAG); + case ISD::ADD: return LowerADD(Op, DAG); case ISD::BRCOND: return LowerBRCOND(Op, DAG); case ISD::LOAD: { LoadSDNode *Load = dyn_cast<LoadSDNode>(Op); @@ -560,6 +561,33 @@ SDValue SITargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { return SDValue(); } +SDValue SITargetLowering::LowerADD(SDValue Op, + SelectionDAG &DAG) const { + if (Op.getValueType() != MVT::i64) + return SDValue(); + + SDLoc DL(Op); + SDValue LHS = Op.getOperand(0); + SDValue RHS = Op.getOperand(1); + + SDValue Zero = DAG.getConstant(0, MVT::i32); + SDValue One = DAG.getConstant(1, MVT::i32); + + SDValue Lo0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, LHS, Zero); + SDValue Hi0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, LHS, One); + + SDValue Lo1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, RHS, Zero); + SDValue Hi1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, RHS, One); + + SDVTList VTList = DAG.getVTList(MVT::i32, MVT::Glue); + + SDValue AddLo = DAG.getNode(ISD::ADDC, DL, VTList, Lo0, Lo1); + SDValue Carry = AddLo.getValue(1); + SDValue AddHi = DAG.getNode(ISD::ADDE, DL, VTList, Hi0, Hi1, Carry); + + return DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, AddLo, AddHi.getValue(0)); +} + /// \brief Helper function for LowerBRCOND static SDNode *findUser(SDValue Value, unsigned Opcode) { diff --git a/lib/Target/R600/SIISelLowering.h b/lib/Target/R600/SIISelLowering.h index 384caf4bc9..9933eced90 100644 --- a/lib/Target/R600/SIISelLowering.h +++ b/lib/Target/R600/SIISelLowering.h @@ -30,6 +30,7 @@ class SITargetLowering : public AMDGPUTargetLowering { SDValue LowerSIGN_EXTEND(SDValue Op, SelectionDAG &DAG) const; SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const; SDValue LowerZERO_EXTEND(SDValue Op, SelectionDAG &DAG) const; + SDValue LowerADD(SDValue Op, SelectionDAG &DAG) const; SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const; SDValue ResourceDescriptorToi128(SDValue Op, SelectionDAG &DAG) const; diff --git a/test/CodeGen/R600/add_i64.ll b/test/CodeGen/R600/add_i64.ll new file mode 100644 index 0000000000..1f846b4ed3 --- /dev/null +++ b/test/CodeGen/R600/add_i64.ll @@ -0,0 +1,45 @@ +; XFAIL: * +; This will fail until i64 add is enabled + +; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck --check-prefix=SI %s + + +declare i32 @llvm.SI.tid() readnone + +; SI-LABEL: @test_i64_vreg: +define void @test_i64_vreg(i64 addrspace(1)* noalias %out, i64 addrspace(1)* noalias %inA, i64 addrspace(1)* noalias %inB) { + %tid = call i32 @llvm.SI.tid() readnone + %a_ptr = getelementptr i64 addrspace(1)* %inA, i32 %tid + %b_ptr = getelementptr i64 addrspace(1)* %inB, i32 %tid + %a = load i64 addrspace(1)* %a_ptr + %b = load i64 addrspace(1)* %b_ptr + %result = add i64 %a, %b + store i64 %result, i64 addrspace(1)* %out + ret void +} + +; SI-LABEL: @test_i64_sreg: +define void @test_i64_sreg(i64 addrspace(1)* noalias %out, i64 %a, i64 %b) { + %result = add i64 %a, %b + store i64 %result, i64 addrspace(1)* %out + ret void +} + +; SI-LABEL: @test_v2i64_sreg: +define void @test_v2i64_sreg(<2 x i64> addrspace(1)* noalias %out, <2 x i64> %a, <2 x i64> %b) { + %result = add <2 x i64> %a, %b + store <2 x i64> %result, <2 x i64> addrspace(1)* %out + ret void +} + +; SI-LABEL: @test_v2i64_vreg: +define void @test_v2i64_vreg(<2 x i64> addrspace(1)* noalias %out, <2 x i64> addrspace(1)* noalias %inA, <2 x i64> addrspace(1)* noalias %inB) { + %tid = call i32 @llvm.SI.tid() readnone + %a_ptr = getelementptr <2 x i64> addrspace(1)* %inA, i32 %tid + %b_ptr = getelementptr <2 x i64> addrspace(1)* %inB, i32 %tid + %a = load <2 x i64> addrspace(1)* %a_ptr + %b = load <2 x i64> addrspace(1)* %b_ptr + %result = add <2 x i64> %a, %b + store <2 x i64> %result, <2 x i64> addrspace(1)* %out + ret void +} |