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| author | Hal Finkel <hfinkel@anl.gov> | 2013-12-14 14:41:55 +0000 |
|---|---|---|
| committer | Hal Finkel <hfinkel@anl.gov> | 2013-12-14 14:41:55 +0000 |
| commit | e74957a7744bcd1a912fc15a915af570bd7a9583 (patch) | |
| tree | 37650e6d85906d817ed50271a2f70c455f776e28 | |
| parent | dd36ddfaec578968b163fc4bbb7148921084aa6e (diff) | |
| download | llvm-e74957a7744bcd1a912fc15a915af570bd7a9583.tar.gz llvm-e74957a7744bcd1a912fc15a915af570bd7a9583.tar.bz2 llvm-e74957a7744bcd1a912fc15a915af570bd7a9583.tar.xz | |
Add release notes for the PowerPC backend
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@197325 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | docs/ReleaseNotes.rst | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/docs/ReleaseNotes.rst b/docs/ReleaseNotes.rst index c6b72f4235..ed7b99fa58 100644 --- a/docs/ReleaseNotes.rst +++ b/docs/ReleaseNotes.rst @@ -110,6 +110,22 @@ For more information on MSA (including documentation for the instruction set), see the `MIPS SIMD page at Imagination Technologies <http://imgtec.com/mips/mips-simd.asp>`_ +PowerPC Target +-------------- + +Changes in the PowerPC backend include: + +* fast-isel support (for faster -O0 code generation) +* many improvements to the builtin assembler +* support for generating unaligned (Altivec) vector loads +* support for generating the fcpsgn instruction +* generate frin for round() (not nearbyint() and rint(), which had been done only in fast-math mode) +* improved instruction scheduling for embedded cores (such as the A2) +* improved prologue/epilogue generation (especially in 32-bit mode) +* support for dynamic stack alignment (and dynamic stack allocations with large alignments) +* improved generation of counter-register-based loops +* bug fixes + SPARC Target ------------ |