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| author | Artyom Skrobov <Artyom.Skrobov@arm.com> | 2013-11-11 19:56:13 +0000 |
|---|---|---|
| committer | Artyom Skrobov <Artyom.Skrobov@arm.com> | 2013-11-11 19:56:13 +0000 |
| commit | ef572e31e210a03c0669e3ed2ed7cf2d789f8599 (patch) | |
| tree | 3e20bbe507846933cc69c33c94b86782062914b4 | |
| parent | 559d409633ce22574dcab56d4f600b6eb1304652 (diff) | |
| download | llvm-ef572e31e210a03c0669e3ed2ed7cf2d789f8599.tar.gz llvm-ef572e31e210a03c0669e3ed2ed7cf2d789f8599.tar.bz2 llvm-ef572e31e210a03c0669e3ed2ed7cf2d789f8599.tar.xz | |
[ARM] Add support for MVFR2 which is new in ARMv8
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194416 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/ARM/ARMInstrVFP.td | 2 | ||||
| -rw-r--r-- | lib/Target/ARM/ARMRegisterInfo.td | 1 | ||||
| -rw-r--r-- | test/MC/ARM/fp-armv8.s | 5 | ||||
| -rw-r--r-- | test/MC/Disassembler/ARM/fp-armv8.txt | 5 | ||||
| -rw-r--r-- | test/MC/Disassembler/ARM/invalid-because-armv7.txt | 6 |
5 files changed, 19 insertions, 0 deletions
diff --git a/lib/Target/ARM/ARMInstrVFP.td b/lib/Target/ARM/ARMInstrVFP.td index ff1087fe65..a8cdc5ca06 100644 --- a/lib/Target/ARM/ARMInstrVFP.td +++ b/lib/Target/ARM/ARMInstrVFP.td @@ -1546,6 +1546,8 @@ let Uses = [FPSCR] in { "vmrs", "\t$Rt, mvfr0", []>; def VMRS_MVFR1 : MovFromVFP<0b0110 /* mvfr1 */, (outs GPR:$Rt), (ins), "vmrs", "\t$Rt, mvfr1", []>; + def VMRS_MVFR2 : MovFromVFP<0b0101 /* mvfr2 */, (outs GPR:$Rt), (ins), + "vmrs", "\t$Rt, mvfr2", []>, Requires<[HasFPARMv8]>; def VMRS_FPINST : MovFromVFP<0b1001 /* fpinst */, (outs GPR:$Rt), (ins), "vmrs", "\t$Rt, fpinst", []>; def VMRS_FPINST2 : MovFromVFP<0b1010 /* fpinst2 */, (outs GPR:$Rt), (ins), diff --git a/lib/Target/ARM/ARMRegisterInfo.td b/lib/Target/ARM/ARMRegisterInfo.td index 90c6a965ac..d0457618ef 100644 --- a/lib/Target/ARM/ARMRegisterInfo.td +++ b/lib/Target/ARM/ARMRegisterInfo.td @@ -172,6 +172,7 @@ def ITSTATE : ARMReg<4, "itstate">; // Special Registers - only available in privileged mode. def FPSID : ARMReg<0, "fpsid">; +def MVFR2 : ARMReg<5, "mvfr2">; def MVFR1 : ARMReg<6, "mvfr1">; def MVFR0 : ARMReg<7, "mvfr0">; def FPEXC : ARMReg<8, "fpexc">; diff --git a/test/MC/ARM/fp-armv8.s b/test/MC/ARM/fp-armv8.s index cba4a5157c..1ffd5902e5 100644 --- a/test/MC/ARM/fp-armv8.s +++ b/test/MC/ARM/fp-armv8.s @@ -122,3 +122,8 @@ @ CHECK: vrintm.f64 d3, d4 @ encoding: [0x44,0x3b,0xbb,0xfe] vrintm.f32 s12, s1 @ CHECK: vrintm.f32 s12, s1 @ encoding: [0x60,0x6a,0xbb,0xfe] + +@ MVFR2 + + vmrs sp, mvfr2 +@ CHECK: vmrs sp, mvfr2 @ encoding: [0x10,0xda,0xf5,0xee] diff --git a/test/MC/Disassembler/ARM/fp-armv8.txt b/test/MC/Disassembler/ARM/fp-armv8.txt index 4d2f8f6881..46a26f5d6d 100644 --- a/test/MC/Disassembler/ARM/fp-armv8.txt +++ b/test/MC/Disassembler/ARM/fp-armv8.txt @@ -153,3 +153,8 @@ 0x60 0x6a 0xbb 0xfe # CHECK: vrintm.f32 s12, s1 + + +0x10 0xa 0xf5 0xee +# CHECK: vmrs r0, mvfr2 + diff --git a/test/MC/Disassembler/ARM/invalid-because-armv7.txt b/test/MC/Disassembler/ARM/invalid-because-armv7.txt index 4bf4833a9a..beed8e4eb0 100644 --- a/test/MC/Disassembler/ARM/invalid-because-armv7.txt +++ b/test/MC/Disassembler/ARM/invalid-because-armv7.txt @@ -18,3 +18,9 @@ [0x41 0x2b 0xb3 0xbe] # CHECK: invalid instruction encoding # CHECK-NEXT: [0x41 0x2b 0xb3 0xbe] + +# Would be vmrs r0, mvfr2 +[0x10 0xa 0xf5 0xee] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x10 0xa 0xf5 0xee] + |