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| author | James Molloy <james.molloy@arm.com> | 2011-10-19 14:11:07 +0000 |
|---|---|---|
| committer | James Molloy <james.molloy@arm.com> | 2011-10-19 14:11:07 +0000 |
| commit | cdd8e46bec4e975d00a5abea808d8eb4138515c5 (patch) | |
| tree | 5feaecc08b9dae81374c129cfe5d28552a998c25 | |
| parent | 40230c4c06e0ad1afbef217229363cab077368b3 (diff) | |
| download | llvm-cdd8e46bec4e975d00a5abea808d8eb4138515c5.tar.gz llvm-cdd8e46bec4e975d00a5abea808d8eb4138515c5.tar.bz2 llvm-cdd8e46bec4e975d00a5abea808d8eb4138515c5.tar.xz | |
Use literal pool loads instead of MOVW/MOVT for materializing global addresses when optimizing for size.
On spec/gcc, this caused a codesize improvement of ~1.9% for ARM mode and ~4.9% for Thumb(2) mode. This is
codesize including literal pools.
The pools themselves doubled in size for ARM mode and quintupled for Thumb mode, leaving suggestion that there
is still perhaps redundancy in LLVM's use of constant pools that could be decreased by sharing entries.
Fixes PR11087.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142530 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/ARM/ARMISelLowering.cpp | 9 | ||||
| -rw-r--r-- | test/CodeGen/ARM/2011-10-18-DisableMovtSize.ll | 27 |
2 files changed, 33 insertions, 3 deletions
diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp index beae30a2a7..34023af084 100644 --- a/lib/Target/ARM/ARMISelLowering.cpp +++ b/lib/Target/ARM/ARMISelLowering.cpp @@ -2103,8 +2103,10 @@ SDValue ARMTargetLowering::LowerGlobalAddressELF(SDValue Op, } // If we have T2 ops, we can materialize the address directly via movt/movw - // pair. This is always cheaper. - if (Subtarget->useMovt()) { + // pair. This is always cheaper in terms of performance, but uses at least 2 + // extra bytes. + if (Subtarget->useMovt() && + !DAG.getMachineFunction().getFunction()->hasFnAttr(Attribute::OptimizeForSize)) { ++NumMovwMovt; // FIXME: Once remat is capable of dealing with instructions with register // operands, expand this into two nodes. @@ -2129,7 +2131,8 @@ SDValue ARMTargetLowering::LowerGlobalAddressDarwin(SDValue Op, ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); // FIXME: Enable this for static codegen when tool issues are fixed. - if (Subtarget->useMovt() && RelocM != Reloc::Static) { + if (Subtarget->useMovt() && RelocM != Reloc::Static && + !DAG.getMachineFunction().getFunction()->hasFnAttr(Attribute::OptimizeForSize)) { ++NumMovwMovt; // FIXME: Once remat is capable of dealing with instructions with register // operands, expand this into two nodes. diff --git a/test/CodeGen/ARM/2011-10-18-DisableMovtSize.ll b/test/CodeGen/ARM/2011-10-18-DisableMovtSize.ll new file mode 100644 index 0000000000..6dae75be91 --- /dev/null +++ b/test/CodeGen/ARM/2011-10-18-DisableMovtSize.ll @@ -0,0 +1,27 @@ +; RUN: llc < %s -mtriple=armv7-apple-darwin | FileCheck %s +; RUN: llc < %s -mtriple=armv7-unknown-linux-eabi | FileCheck %s + +; Check that when optimizing for size, a literal pool load is used +; instead of the (potentially faster) movw/movt pair when loading +; a large constant. + +@x = global i32* inttoptr (i32 305419888 to i32*), align 4 + +define i32 @f() optsize { + ; CHECK: f: + ; CHECK: ldr r{{.}}, {{.?}}LCPI{{.}}_{{.}} + ; CHECK: ldr r{{.}}, [{{(pc, )?}}r{{.}}] + ; CHECK: ldr r{{.}}, [r{{.}}] + %1 = load i32** @x, align 4 + %2 = load i32* %1 + ret i32 %2 +} + +define i32 @g() { + ; CHECK: g: + ; CHECK: movw + ; CHECK: movt + %1 = load i32** @x, align 4 + %2 = load i32* %1 + ret i32 %2 +} |