Merge branch 'release-3.2' into embtk-support-release-3.2

4 files changed, 117 insertions, 64 deletions

diff --git a/docs/ReleaseNotes.html b/docs/ReleaseNotes.html
index a84fabaccf..99bdf613a0 100644
--- a/docs/ReleaseNotes.html
+++ b/docs/ReleaseNotes.html
@@ -29,12 +29,6 @@
   <p>Written by the <a href="http://llvm.org/">LLVM Team</a></p>
 </div>
 
-<h1 style="color:red">These are in-progress notes for the upcoming LLVM 3.2
-release.<br>
-You may prefer the
-<a href="http://llvm.org/releases/3.1/docs/ReleaseNotes.html">LLVM 3.1
-Release Notes</a>.</h1>
-
 <!-- *********************************************************************** -->
 <h2>
   <a name="intro">Introduction</a>
@@ -46,7 +40,7 @@ Release Notes</a>.</h1>
 <p>This document contains the release notes for the LLVM Compiler
    Infrastructure, release 3.2.  Here we describe the status of LLVM, including
    major improvements from the previous release, improvements in various
-   subprojects of LLVM, and some of the current users of the code.  All LLVM
+   sub-projects of LLVM, and some of the current users of the code.  All LLVM
    releases may be downloaded from the <a href="http://llvm.org/releases/">LLVM
    releases web site</a>.</p>
 
@@ -77,7 +71,7 @@ Release Notes</a>.</h1>
    code generators and supporting tools, as well as Clang, DragonEgg and 
    compiler-rt sub-project repositories. In addition to this code, the LLVM 
    Project includes other sub-projects that are in development. Here we 
-   include updates on these subprojects.</p>
+   include updates on these sub-projects.</p>
 
 <!--=========================================================================-->
 <h3>
@@ -91,18 +85,18 @@ Release Notes</a>.</h1>
    experience through expressive diagnostics, a high level of conformance to
    language standards, fast compilation, and low memory use. Like LLVM, Clang
    provides a modular, library-based architecture that makes it suitable for
-   creating or integrating with other development tools. Clang is considered a
-   production-quality compiler for C, Objective-C, C++ and Objective-C++ on x86
-   (32- and 64-bit), and for Darwin/ARM targets.</p>
+   creating or integrating with other development tools.</p>
 
 <p>In the LLVM 3.2 time-frame, the Clang team has made many improvements.
    Highlights include:</p>
 <ul>
-  <li>...</li>
+  <li>Improvements to Clang's diagnostics</li>
+  <li>Support for tls_model attribute</li>
+  <li>Type safety attributes</li>
 </ul>
 
 <p>For more details about the changes to Clang since the 3.1 release, see the
-   <a href="http://clang.llvm.org/docs/ReleaseNotes.html">Clang release
+   <a href="http://llvm.org/releases/3.2/tools/clang/docs/ReleaseNotes.html">Clang 3.2 release
    notes.</a></p>
 
 <p>If Clang rejects your code but another compiler accepts it, please take a
@@ -142,7 +136,8 @@ Release Notes</a>.</h1>
 
 <div>
 
-<p>The new LLVM <a href="http://compiler-rt.llvm.org/">compiler-rt project</a>
+
+<p>The LLVM <a href="http://compiler-rt.llvm.org/">compiler-rt project</a>
    is a simple library that provides an implementation of the low-level
    target-specific hooks required by code generation and other runtime
    components.  For example, when compiling for a 32-bit target, converting a
@@ -154,7 +149,12 @@ Release Notes</a>.</h1>
 <p>The 3.2 release has the following notable changes:</p>
 
 <ul>
-  <li>...</li>
+  <li><a href="http://llvm.org/releases/3.2/tools/clang/docs/ThreadSanitizer.html">ThreadSanitizer (TSan)</a> - data race detector run-time library for C/C++ has been added.</li>
+  <li>Improvemens to <a href="http://llvm.org/releases/3.2/tools/clang/docs/AddressSanitizer.html">AddressSanitizer</a> including: increasing stack size limit to 256MB,
+          better portability (Android NDK), support for cmake based builds, enhanced error reporting.</li>
+
+  <li>Added support for A6 'Swift' CPU.</li>
+  <li><code>divsi3</code> function has been enhanced to take advantage of a hardware unsigned divide when it is available.</li>
 </ul>
 
 </div>
@@ -228,14 +228,19 @@ Release Notes</a>.</h1>
 
 <p><a href="http://polly.llvm.org/">Polly</a> is an <em>experimental</em>
   optimizer for data locality and parallelism. It currently provides high-level
-  loop optimizations and automatic parallelisation (using the OpenMP run time).
+  loop optimizations and automatic parallelization (using the OpenMP run time).
   Work in the area of automatic SIMD and accelerator code generation was
   started.</p>
 
 <p>Within the LLVM 3.2 time-frame there were the following highlights:</p>
 
 <ul>
-  <li>...</li>
+  <li>isl, the integer set library used by Polly, was relicensed under the MIT license.</li>
+  <li>isl based code generation.</li>
+  <li>MIT licensed replacement for CLooG (LGPLv2).</li>
+  <li>Fine grained option handling (separation of core and border computations, control overhead vs. code size).</li>
+  <li>Support for FORTRAN and Dragonegg.</li>
+  <li>OpenMP code generation fixes.</li>
 </ul>
 
 </div>
@@ -275,7 +280,7 @@ Release Notes</a>.</h1>
    AUdio STream. Its programming model combines two approaches: functional
    programming and block diagram composition. In addition with the C, C++, Java,
    JavaScript output formats, the Faust compiler can generate LLVM bitcode, and
-   works with LLVM 2.7-3.1.</p>
+   works with LLVM 2.7-3.2.</p>
 
 </div>
 
@@ -433,9 +438,9 @@ Release Notes</a>.</h1>
 <p>LLVM 3.2 includes several major changes and big features:</p>
 
 <ul>
-  <li>...</li>
-  <li>New NVPTX back-end (replacing existing PTX back-end) based on NVIDIA
-      sources</li>
+  <li>Loop Vectorizer.</li>
+  <li>New implementation of SROA.</li>
+  <li>New NVPTX back-end (replacing existing PTX back-end) based on NVIDIA sources.</li>
 </ul>
 
 </div>
@@ -454,7 +459,10 @@ Release Notes</a>.</h1>
 <ul>
   <li>Thread local variables may have a specified TLS model. See the
   <a href="LangRef.html#globalvars">Language Reference Manual</a>.</li>
-  <li>...</li>
+  <li>'TYPE_CODE_FUNCTION_OLD' type code and autoupgrade code for old function attributes format has been removed.</li>
+  <li>Internal representation of the Attributes class has been converted into a pointer to an
+         opaque object that's uniqued by and stored in the LLVMContext object. 
+         The Attributes class then becomes a thin wrapper around this opaque object.</li>
 </ul>
 
 </div>
@@ -492,7 +500,7 @@ Release Notes</a>.</h1>
     <ul>
     <li>The inner most loops must have a single basic block.</li>
     <li>The number of iterations are known before the loop starts to execute.</li>
-    <li>The loop counter needs to be incrimented by one.</li>
+    <li>The loop counter needs to be incremented by one.</li>
     <li>The loop trip count <b>can</b> be a variable.</li>
     <li>Loops do <b>not</b> need to start at zero.</li>
     <li>The induction variable can be used inside the loop.</li>
@@ -527,8 +535,19 @@ Release Notes</a>.</h1>
    <a href="http://blog.llvm.org/2010/04/intro-to-llvm-mc-project.html">Intro
    to the LLVM MC Project Blog Post</a>.</p>
 
-<ul>
-  <li>...</li>
+<ul>    
+  <li> Added support for following assembler directives: <code>.ifb</code>, <code>.ifnb</code>, <code>.ifc</code>, 
+          <code>.ifnc</code>, <code>.purgem</code>, <code>.rept</code> and <code>.version</code> (ELF) as well as Darwin specific
+	<code>.pushsection</code>, <code>.popsection</code> and  <code>.previous</code> .</li>
+  <li>Enhanced handling of <code>.lcomm directive</code>.</li>
+  <li>MS style inline assembler: added implementation of the offset and TYPE operators.</li>
+  <li>Targets can specify minimum supported NOP size for NOP padding.</li>
+  <li>ELF improvements: added support for generating ELF objects on Windows.</li>
+  <li>MachO improvements:  symbol-difference variables are marked as N_ABS, added direct-to-object attribute for data-in-code markers.</li>
+  <li>Added support for annotated disassembly output for x86 and arm targets.</li>
+  <li>Arm support has been improved by adding support for ARM TARGET2 relocation
+          and fixing hadling of ARM-style "$d.*" labels.</li>
+   <li>Implemented local-exec TLS on PowerPC.</li>
 </ul>
 
 </div>
@@ -591,7 +610,7 @@ Release Notes</a>.</h1>
 <p>New features and major changes in the X86 target include:</p>
 
 <ul>
-  <li>...</li>
+  <li>Small codegen optimizations, especially for AVX2.</li>
 </ul>
 
 </div>
@@ -606,7 +625,7 @@ Release Notes</a>.</h1>
 <p>New features of the ARM target include:</p>
 
 <ul>
-  <li>...</li>
+  <li>Support and performance tuning for the A6 'Swift' CPU.</li>
 </ul>
 
 <!--_________________________________________________________________________-->
@@ -643,7 +662,29 @@ Release Notes</a>.</h1>
 <p>New features and major changes in the MIPS target include:</p>
 
 <ul>
-  <li>...</li>
+  <li>Integrated assembler support: 
+         MIPS32 works for both PIC and static, known limitation is the PR14456 where 
+         R_MIPS_GPREL16 relocation is generated with the wrong addend.
+         MIPS64 support is incomplete, for example exception handling is not working.</li>
+   <li>Support for fast calling convention has been added.</li>
+   <li>Support for Android MIPS toolchain has been added to clang driver.</li>
+   <li>Added clang driver support for MIPS N32 ABI through "-mabi=n32" option.</li>
+   <li>MIPS32 and MIPS64 disassembler has been implemented.</li>
+   <li>Support for compiling programs with large GOTs (exceeding 64kB in size) has been added 
+	through llc option "-mxgot".</li>
+  <li>Added experimental support for MIPS32 DSP intrinsics.</li>
+  <li>Experimental support for MIPS16 with following limitations: only soft float is supported,
+         C++ exceptions are not supported, large stack frames (> 32000 bytes) are not supported,
+         direct object code emission is not supported only .s .</li>
+  <li>Standalone assembler (llvm-mc):  implementation is in progress and considered experimental.</li>
+  <li>All classic JIT and MCJIT tests pass on Little and Big Endian MIPS32 platforms.</li>
+  <li>Inline asm support: all common constraints and operand modifiers have been implemented.</li>
+  <li>Added tail call optimization support, use llc option "-enable-mips-tail-calls"
+      or clang options "-mllvm -enable-mips-tail-calls"to enable it.</li>
+  <li>Improved register allocation by removing registers $fp, $gp, $ra and $at from the list of reserved registers.</li>
+  <li>Long branch expansion pass has been implemented, which expands branch
+      instructions with offsets that do not fit in the 16-bit field.</li>
+  <li>Cavium Octeon II board is used for testing builds (llvm-mips-linux builder).</li>
 </ul>
 
 </div>
@@ -655,7 +696,6 @@ Release Notes</a>.</h1>
 
 <div>
 
-<ul>
 <p>Many fixes and changes across LLVM (and Clang) for better compliance with
    the 64-bit PowerPC ELF Application Binary Interface, interoperability with
    GCC, and overall 64-bit PowerPC support.   Some highlights include:</p>
@@ -684,7 +724,6 @@ Release Notes</a>.</h1>
 <p>There have also been code generation improvements for both 32- and 64-bit
    code. Instruction scheduling support for the Freescale e500mc and e5500
    cores has been added.</p>
-</ul>
 
 </div>
 
@@ -734,9 +773,11 @@ Release Notes</a>.</h1>
    from the previous release.</p>
 
 <ul>
-  <li>...</li>
-</ul>
-
+<li>llvm-ld and llvm-stub have been removed, llvm-ld functionality can be partially replaced by 
+        llvm-link | opt | {llc | as, llc -filetype=obj} | ld, or fully replaced by Clang. </li>
+<li>MCJIT: added support for inline assembly (requires asm parser), added faux remote target execution to lli option '-remote-mcjit'.</li>
+</ul> 
+ 
 </div>
 
 <!--=========================================================================-->
@@ -770,34 +811,22 @@ to remove a dependency on Target. </p>
 
 <div>
 
-<p>In addition, some tools have changed in this release. Some of the changes
-   are:</p>
+<p>In addition, some tools have changed in this release. Some of the changes are:</p>
 
 <ul>
-  <li>...</li>
+<li>opt: added support for '-mtriple' option.</li>
+<li>llvm-mc : - added '-disassemble' support for '-show-inst' and '-show-encoding' options, added '-edis' option to produce annotated 
+        disassembly output for X86 and ARM targets.</li>
+<li>libprofile: allows the profile data file name to be specified by the LLVMPROF_OUTPUT environment variable.</li>
+<li>llvm-objdump: has been changed to display available targets, '-arch' option accepts x86 and x86-64 as valid arch names.</li>
+<li>llc and opt: added FMA formation from pairs of FADD + FMUL or FSUB + FMUL enabled by option '-enable-excess-fp-precision' or option '-enable-unsafe-fp-math',
+       option '-fp-contract' controls the creation by optimizations of fused FP by selecting Fast, Standard, or Strict mode.</li>
+<li>llc: object file output from llc is no longer considered experimental.</li>
 </ul>
 
 </div>
 
 
-<!--=========================================================================-->
-<h3>
-<a name="python">Python Bindings</a>
-</h3>
-
-<div>
-
-<p>Officially supported Python bindings have been added! Feature support is far
-   from complete. The current bindings support interfaces to:</p>
-
-<ul>
-  <li>...</li>
-</ul>
-
-</div>
-
-</div>
-
 <!-- *********************************************************************** -->
 <h2>
   <a name="knownproblems">Known Problems</a>
@@ -818,7 +847,7 @@ to remove a dependency on Target. </p>
   <p>Known problem areas include:</p>
 
 <ul>
-  <li>The CellSPU, MSP430, and XCore backends are experimental.</li>
+  <li>The CellSPU, MSP430, and XCore backends are experimental, and the CellSPU backend will be removed in LLVM 3.3.</li>
 
   <li>The integrated assembler, disassembler, and JIT is not supported by
       several targets. If an integrated assembler is not supported, then a
diff --git a/lib/Transforms/Scalar/SROA.cpp b/lib/Transforms/Scalar/SROA.cpp
index 062ec05342..2d518f735b 100644
--- a/lib/Transforms/Scalar/SROA.cpp
+++ b/lib/Transforms/Scalar/SROA.cpp
@@ -2201,7 +2201,7 @@ static bool isIntegerWideningViable(const DataLayout &TD,
       if (RelBegin == 0 && RelEnd == Size)
         WholeAllocaOp = true;
       if (IntegerType *ITy = dyn_cast<IntegerType>(LI->getType())) {
-        if (ITy->getBitWidth() < TD.getTypeStoreSize(ITy))
+        if (ITy->getBitWidth() < TD.getTypeStoreSizeInBits(ITy))
           return false;
         continue;
       }
@@ -2217,7 +2217,7 @@ static bool isIntegerWideningViable(const DataLayout &TD,
       if (RelBegin == 0 && RelEnd == Size)
         WholeAllocaOp = true;
       if (IntegerType *ITy = dyn_cast<IntegerType>(ValueTy)) {
-        if (ITy->getBitWidth() < TD.getTypeStoreSize(ITy))
+        if (ITy->getBitWidth() < TD.getTypeStoreSizeInBits(ITy))
           return false;
         continue;
       }
diff --git a/test/Transforms/SROA/basictest.ll b/test/Transforms/SROA/basictest.ll
index a291c39b33..9fe926ee2c 100644
--- a/test/Transforms/SROA/basictest.ll
+++ b/test/Transforms/SROA/basictest.ll
@@ -1147,3 +1147,32 @@ define void @PR14465() {
   ret void
 ; CHECK: ret
 }
+
+define void @PR14548(i1 %x) {
+; Handle a mixture of i1 and i8 loads and stores to allocas. This particular
+; pattern caused crashes and invalid output in the PR, and its nature will
+; trigger a mixture in several permutations as we resolve each alloca
+; iteratively.
+; Note that we don't do a particularly good *job* of handling these mixtures,
+; but the hope is that this is very rare.
+; CHECK: @PR14548
+
+entry:
+  %a = alloca <{ i1 }>, align 8
+  %b = alloca <{ i1 }>, align 8
+; Nothing of interest is simplified here.
+; CHECK: alloca
+; CHECK: alloca
+
+  %b.i1 = bitcast <{ i1 }>* %b to i1*
+  store i1 %x, i1* %b.i1, align 8
+  %b.i8 = bitcast <{ i1 }>* %b to i8*
+  %foo = load i8* %b.i8, align 1
+
+  %a.i8 = bitcast <{ i1 }>* %a to i8*
+  call void @llvm.memcpy.p0i8.p0i8.i32(i8* %a.i8, i8* %b.i8, i32 1, i32 1, i1 false) nounwind
+  %bar = load i8* %a.i8, align 1
+  %a.i1 = getelementptr inbounds <{ i1 }>* %a, i32 0, i32 0
+  %baz = load i1* %a.i1, align 1
+  ret void
+}
diff --git a/test/Transforms/SROA/big-endian.ll b/test/Transforms/SROA/big-endian.ll
index ce82d1f30b..1ac6d25d63 100644
--- a/test/Transforms/SROA/big-endian.ll
+++ b/test/Transforms/SROA/big-endian.ll
@@ -82,14 +82,9 @@ entry:
 
   %a0i16ptr = bitcast i8* %a0ptr to i16*
   store i16 1, i16* %a0i16ptr
-; CHECK:      %[[mask0:.*]] = and i16 1, -16
-
-  %a1i4ptr = bitcast i8* %a1ptr to i4*
-  store i4 1, i4* %a1i4ptr
-; CHECK-NEXT: %[[insert0:.*]] = or i16 %[[mask0]], 1
 
   store i8 1, i8* %a2ptr
-; CHECK-NEXT: %[[mask1:.*]] = and i40 undef, 4294967295
+; CHECK:      %[[mask1:.*]] = and i40 undef, 4294967295
 ; CHECK-NEXT: %[[insert1:.*]] = or i40 %[[mask1]], 4294967296
 
   %a3i24ptr = bitcast i8* %a3ptr to i24*
@@ -110,7 +105,7 @@ entry:
   %ai = load i56* %aiptr
   %ret = zext i56 %ai to i64
   ret i64 %ret
-; CHECK-NEXT: %[[ext4:.*]] = zext i16 %[[insert0]] to i56
+; CHECK-NEXT: %[[ext4:.*]] = zext i16 1 to i56
 ; CHECK-NEXT: %[[shift4:.*]] = shl i56 %[[ext4]], 40
 ; CHECK-NEXT: %[[mask4:.*]] = and i56 %[[insert3]], 1099511627775
 ; CHECK-NEXT: %[[insert4:.*]] = or i56 %[[mask4]], %[[shift4]]