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| author | Craig Topper <craig.topper@gmail.com> | 2012-11-10 09:25:36 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@gmail.com> | 2012-11-10 09:25:36 +0000 |
| commit | 52ea24508368167b2ba8eb62fadcb1dcf54a0da2 (patch) | |
| tree | 24a5b49e0bfb0ed2c1c54d03cff624d22ea123f1 | |
| parent | 68b094f83da09c0e78a30f5e5ad8d714cd744653 (diff) | |
| download | llvm-52ea24508368167b2ba8eb62fadcb1dcf54a0da2.tar.gz llvm-52ea24508368167b2ba8eb62fadcb1dcf54a0da2.tar.bz2 llvm-52ea24508368167b2ba8eb62fadcb1dcf54a0da2.tar.xz | |
Remove unnecessary subtraction and addition by 1 around a couple for loops.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167673 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/X86/X86ISelLowering.cpp | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index fc1ca5c8aa..e6c61d16bd 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -12858,9 +12858,9 @@ static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB, DebugLoc dl = MI->getDebugLoc(); MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc)); - unsigned NumArgs = MI->getNumOperands() - 1; - for (unsigned i = 0; i < NumArgs; ++i) { - MachineOperand &Op = MI->getOperand(i+1); + unsigned NumArgs = MI->getNumOperands(); + for (unsigned i = 1; i < NumArgs; ++i) { + MachineOperand &Op = MI->getOperand(i); if (!(Op.isReg() && Op.isImplicit())) MIB.addOperand(Op); } @@ -12895,9 +12895,9 @@ static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB, DebugLoc dl = MI->getDebugLoc(); MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc)); - unsigned NumArgs = MI->getNumOperands() - 1; // remove the results - for (unsigned i = 0; i < NumArgs; ++i) { - MachineOperand &Op = MI->getOperand(i+1); + unsigned NumArgs = MI->getNumOperands(); // remove the results + for (unsigned i = 1; i < NumArgs; ++i) { + MachineOperand &Op = MI->getOperand(i); if (!(Op.isReg() && Op.isImplicit())) MIB.addOperand(Op); } |