diff options
| author | Bill Wendling <isanbard@gmail.com> | 2013-12-09 08:56:18 +0000 |
|---|---|---|
| committer | Bill Wendling <isanbard@gmail.com> | 2013-12-09 08:56:18 +0000 |
| commit | 7d9c02dc620ea5f5cdf2dc0bd0f03d9370f845d3 (patch) | |
| tree | 6ebc7804ce4434fd83f8ec25cd2cdf7e5cf3acae | |
| parent | 571a02f291b051b22d804f90257e2623cbacd7ec (diff) | |
| download | llvm-7d9c02dc620ea5f5cdf2dc0bd0f03d9370f845d3.tar.gz llvm-7d9c02dc620ea5f5cdf2dc0bd0f03d9370f845d3.tar.bz2 llvm-7d9c02dc620ea5f5cdf2dc0bd0f03d9370f845d3.tar.xz | |
Merging r196751:
------------------------------------------------------------------------
r196751 | venkatra | 2013-12-08 20:02:15 -0800 (Sun, 08 Dec 2013) | 3 lines
[Sparc]: Implement getSetCCResultType() in SparcTargetLowering so that umulo/smulo can be lowered on sparcv9 without an assertion error.
------------------------------------------------------------------------
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196766 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/Sparc/SparcISelLowering.cpp | 6 | ||||
| -rw-r--r-- | lib/Target/Sparc/SparcISelLowering.h | 3 | ||||
| -rw-r--r-- | test/CodeGen/SPARC/64cond.ll | 14 |
3 files changed, 23 insertions, 0 deletions
diff --git a/lib/Target/Sparc/SparcISelLowering.cpp b/lib/Target/Sparc/SparcISelLowering.cpp index c01b00e791..64625f7018 100644 --- a/lib/Target/Sparc/SparcISelLowering.cpp +++ b/lib/Target/Sparc/SparcISelLowering.cpp @@ -1607,6 +1607,12 @@ const char *SparcTargetLowering::getTargetNodeName(unsigned Opcode) const { } } +EVT SparcTargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const { + if (!VT.isVector()) + return MVT::i32; + return VT.changeVectorElementTypeToInteger(); +} + /// isMaskedValueZeroForTargetNode - Return true if 'Op & Mask' is known to /// be zero. Op is expected to be a target specific node. Used by DAG /// combiner. diff --git a/lib/Target/Sparc/SparcISelLowering.h b/lib/Target/Sparc/SparcISelLowering.h index 8d27caaf15..2659fc8950 100644 --- a/lib/Target/Sparc/SparcISelLowering.h +++ b/lib/Target/Sparc/SparcISelLowering.h @@ -79,6 +79,9 @@ namespace llvm { virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const; virtual MVT getScalarShiftAmountTy(EVT LHSTy) const { return MVT::i32; } + /// getSetCCResultType - Return the ISD::SETCC ValueType + virtual EVT getSetCCResultType(LLVMContext &Context, EVT VT) const; + virtual SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, diff --git a/test/CodeGen/SPARC/64cond.ll b/test/CodeGen/SPARC/64cond.ll index bdc5e70a2d..7451b04ead 100644 --- a/test/CodeGen/SPARC/64cond.ll +++ b/test/CodeGen/SPARC/64cond.ll @@ -109,3 +109,17 @@ entry: %rv = select i1 %tobool, i64 123, i64 0 ret i64 %rv } + +; CHECK-LABEL: setcc_resultty +; CHECK: cmp +; CHECK: movne %xcc, 1, [[R:%[gilo][0-7]]] +; CHECK: or [[R]], %i1, %i0 + +define i1 @setcc_resultty(i64 %a, i1 %b) { + %a0 = tail call { i64, i1 } @llvm.umul.with.overflow.i64(i64 %a, i64 32) + %a1 = extractvalue { i64, i1 } %a0, 1 + %a4 = or i1 %a1, %b + ret i1 %a4 +} + +declare { i64, i1 } @llvm.umul.with.overflow.i64(i64, i64) |