diff options
author | Elena Demikhovsky <elena.demikhovsky@intel.com> | 2014-02-10 07:02:39 +0000 |
---|---|---|
committer | Elena Demikhovsky <elena.demikhovsky@intel.com> | 2014-02-10 07:02:39 +0000 |
commit | 27ef6eec41f28383581cd4ce9c7d64bba3e5a101 (patch) | |
tree | e2e491c977547ebc98be6bfd08798c087f377cec | |
parent | ced275628057b8ed3679ff7df25a61dfcc04a645 (diff) | |
download | llvm-27ef6eec41f28383581cd4ce9c7d64bba3e5a101.tar.gz llvm-27ef6eec41f28383581cd4ce9c7d64bba3e5a101.tar.bz2 llvm-27ef6eec41f28383581cd4ce9c7d64bba3e5a101.tar.xz |
AVX-512: Fixed extract_vector_elt for v16i1 and v8i1 vectors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201066 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r-- | lib/Target/X86/X86ISelLowering.cpp | 14 | ||||
-rw-r--r-- | lib/Target/X86/X86ISelLowering.h | 2 | ||||
-rw-r--r-- | lib/Target/X86/X86InstrAVX512.td | 4 | ||||
-rw-r--r-- | lib/Target/X86/X86InstrFragmentsSIMD.td | 2 | ||||
-rw-r--r-- | test/CodeGen/X86/avx512-insert-extract.ll | 17 |
5 files changed, 29 insertions, 10 deletions
diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index a945284fa6..2e9d574407 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -7751,14 +7751,12 @@ static SDValue ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) { } unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue(); - if (IdxVal) { - unsigned MaxSift = VecVT.getSizeInBits() - 1; - Vec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, Vec, - DAG.getConstant(MaxSift - IdxVal, MVT::i8)); - Vec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, Vec, - DAG.getConstant(MaxSift, MVT::i8)); - } - return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i1, Vec, + unsigned MaxSift = VecVT.getSizeInBits() - 1; + Vec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, Vec, + DAG.getConstant(MaxSift - IdxVal, MVT::i8)); + Vec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, Vec, + DAG.getConstant(MaxSift, MVT::i8)); + return DAG.getNode(X86ISD::VEXTRACT, dl, MVT::i1, Vec, DAG.getIntPtrConstant(0)); } diff --git a/lib/Target/X86/X86ISelLowering.h b/lib/Target/X86/X86ISelLowering.h index 5d00e26e7c..6ea060ba3b 100644 --- a/lib/Target/X86/X86ISelLowering.h +++ b/lib/Target/X86/X86ISelLowering.h @@ -340,7 +340,9 @@ namespace llvm { VBROADCAST, // masked broadcast VBROADCASTM, + // Insert/Extract vector element VINSERT, + VEXTRACT, // PMULUDQ - Vector multiply packed unsigned doubleword integers PMULUDQ, diff --git a/lib/Target/X86/X86InstrAVX512.td b/lib/Target/X86/X86InstrAVX512.td index 2f9c0578cf..edcc32751d 100644 --- a/lib/Target/X86/X86InstrAVX512.td +++ b/lib/Target/X86/X86InstrAVX512.td @@ -983,9 +983,9 @@ let Predicates = [HasAVX512] in { (KMOVWrk (COPY_TO_REGCLASS VK8:$src, VK16)), sub_8bit)>; - def : Pat<(i1 (extractelt VK16:$src, (iPTR 0))), + def : Pat<(i1 (X86Vextract VK16:$src, (iPTR 0))), (COPY_TO_REGCLASS VK16:$src, VK1)>; - def : Pat<(i1 (extractelt VK8:$src, (iPTR 0))), + def : Pat<(i1 (X86Vextract VK8:$src, (iPTR 0))), (COPY_TO_REGCLASS VK8:$src, VK1)>; } diff --git a/lib/Target/X86/X86InstrFragmentsSIMD.td b/lib/Target/X86/X86InstrFragmentsSIMD.td index c029bef663..486e5a9619 100644 --- a/lib/Target/X86/X86InstrFragmentsSIMD.td +++ b/lib/Target/X86/X86InstrFragmentsSIMD.td @@ -236,6 +236,8 @@ def X86VBroadcast : SDNode<"X86ISD::VBROADCAST", SDTVBroadcast>; def X86VBroadcastm : SDNode<"X86ISD::VBROADCASTM", SDTVBroadcastm>; def X86Vinsert : SDNode<"X86ISD::VINSERT", SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisPtrTy<3>]>, []>; +def X86Vextract : SDNode<"X86ISD::VEXTRACT", SDTypeProfile<1, 2, + [SDTCisVec<1>, SDTCisPtrTy<2>]>, []>; def X86Blendi : SDNode<"X86ISD::BLENDI", SDTBlend>; def X86Fmadd : SDNode<"X86ISD::FMADD", SDTFma>; diff --git a/test/CodeGen/X86/avx512-insert-extract.ll b/test/CodeGen/X86/avx512-insert-extract.ll index 64f2a19700..f8a84bb1f2 100644 --- a/test/CodeGen/X86/avx512-insert-extract.ll +++ b/test/CodeGen/X86/avx512-insert-extract.ll @@ -117,3 +117,20 @@ define <16 x i32> @test11(<16 x i32>%a, <16 x i32>%b) { %c = add <16 x i32>%b, %a ret <16 x i32>%c } + +;CHECK-LABEL: test12 +;CHECK: vpcmpgtq +;CKECK: kshiftlw $15 +;CKECK: kshiftrw $15 +;CHECK: kortestw +;CHECK: ret + +define i64 @test12(<16 x i64>%a, <16 x i64>%b, i64 %a1, i64 %b1) { + + %cmpvector_func.i = icmp slt <16 x i64> %a, %b + %extract24vector_func.i = extractelement <16 x i1> %cmpvector_func.i, i32 0 + %res = select i1 %extract24vector_func.i, i64 %a1, i64 %b1 + ret i64 %res +} + + |