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authorDavid Woodhouse <dwmw2@infradead.org>2014-01-08 18:38:26 +0000
committerDavid Woodhouse <dwmw2@infradead.org>2014-01-08 18:38:26 +0000
commitadc537e74b719db8abc42ec57f7bdb25176d8569 (patch)
tree2c16855fef37b4b1dbd00f9fcda2d7807bb91bc0
parent638e97f13512b8424fac28e4ed79964300bcf8b0 (diff)
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[x86] Remove OpSize16 flag from MOV32r0
It's not a real instruction any more and doesn't need encoding information. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198778 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r--lib/Target/X86/X86InstrCompiler.td3
1 files changed, 1 insertions, 2 deletions
diff --git a/lib/Target/X86/X86InstrCompiler.td b/lib/Target/X86/X86InstrCompiler.td
index 8294b5881f..745eed4d1f 100644
--- a/lib/Target/X86/X86InstrCompiler.td
+++ b/lib/Target/X86/X86InstrCompiler.td
@@ -223,8 +223,7 @@ def MORESTACK_RET_RESTORE_R10 : I<0, Pseudo, (outs), (ins),
let Defs = [EFLAGS], isReMaterializable = 1, isAsCheapAsAMove = 1,
isPseudo = 1 in
def MOV32r0 : I<0, Pseudo, (outs GR32:$dst), (ins), "",
- [(set GR32:$dst, 0)], IIC_ALU_NONMEM>, OpSize16,
- Sched<[WriteZero]>;
+ [(set GR32:$dst, 0)], IIC_ALU_NONMEM>, Sched<[WriteZero]>;
// Other widths can also make use of the 32-bit xor, which may have a smaller
// encoding and avoid partial register updates.