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authorTim Northover <tnorthover@apple.com>2014-03-29 10:18:08 +0000
committerTim Northover <tnorthover@apple.com>2014-03-29 10:18:08 +0000
commit7b837d8c75f78fe55c9b348b9ec2281169a48d2a (patch)
treee8e01e73cf4d0723a13e49e4b5d8a66f896d184f /configure
parent69bd9577fc423edea13479eaacf7b1844faa6c6a (diff)
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ARM64: initial backend import
This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205090 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'configure')
-rwxr-xr-xconfigure13
1 files changed, 8 insertions, 5 deletions
diff --git a/configure b/configure
index 186524764a..778aa189d5 100755
--- a/configure
+++ b/configure
@@ -1447,9 +1447,9 @@ Optional Features:
Enable crash handling overrides (default is YES)
--enable-targets Build specific host targets: all or
target1,target2,... Valid targets are: host, x86,
- x86_64, sparc, powerpc, arm, aarch64, mips, hexagon,
- xcore, msp430, nvptx, systemz, r600, and cpp
- (default=all)
+ x86_64, sparc, powerpc, arm64, arm, aarch64, mips,
+ hexagon, xcore, msp430, nvptx, systemz, r600, and
+ cpp (default=all)
--enable-experimental-targets
Build experimental host targets: disable or
target1,target2,... (default=disable)
@@ -4151,6 +4151,7 @@ else
amd64-* | x86_64-*) llvm_cv_target_arch="x86_64" ;;
sparc*-*) llvm_cv_target_arch="Sparc" ;;
powerpc*-*) llvm_cv_target_arch="PowerPC" ;;
+ arm64*-*) llvm_cv_target_arch="ARM64" ;;
arm*-*) llvm_cv_target_arch="ARM" ;;
aarch64*-*) llvm_cv_target_arch="AArch64" ;;
mips-* | mips64-*) llvm_cv_target_arch="Mips" ;;
@@ -4187,6 +4188,7 @@ case $host in
amd64-* | x86_64-*) host_arch="x86_64" ;;
sparc*-*) host_arch="Sparc" ;;
powerpc*-*) host_arch="PowerPC" ;;
+ arm64*-*) host_arch="ARM64" ;;
arm*-*) host_arch="ARM" ;;
aarch64*-*) host_arch="AArch64" ;;
mips-* | mips64-*) host_arch="Mips" ;;
@@ -5120,7 +5122,7 @@ else
esac
fi
-TARGETS_WITH_JIT="AArch64 ARM Mips PowerPC SystemZ X86"
+TARGETS_WITH_JIT="AArch64 ARM ARM64 Mips PowerPC SystemZ X86"
TARGETS_WITH_JIT=$TARGETS_WITH_JIT
@@ -5357,7 +5359,7 @@ _ACEOF
fi
-ALL_TARGETS="X86 Sparc PowerPC AArch64 ARM Mips XCore MSP430 CppBackend NVPTX Hexagon SystemZ R600"
+ALL_TARGETS="X86 Sparc PowerPC AArch64 ARM ARM64 Mips XCore MSP430 CppBackend NVPTX Hexagon SystemZ R600"
ALL_TARGETS=$ALL_TARGETS
@@ -5381,6 +5383,7 @@ case "$enableval" in
sparc) TARGETS_TO_BUILD="Sparc $TARGETS_TO_BUILD" ;;
powerpc) TARGETS_TO_BUILD="PowerPC $TARGETS_TO_BUILD" ;;
aarch64) TARGETS_TO_BUILD="AArch64 $TARGETS_TO_BUILD" ;;
+ arm64) TARGETS_TO_BUILD="ARM64 $TARGETS_TO_BUILD" ;;
arm) TARGETS_TO_BUILD="ARM $TARGETS_TO_BUILD" ;;
mips) TARGETS_TO_BUILD="Mips $TARGETS_TO_BUILD" ;;
mipsel) TARGETS_TO_BUILD="Mips $TARGETS_TO_BUILD" ;;