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author | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2012-02-10 18:58:34 +0000 |
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committer | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2012-02-10 18:58:34 +0000 |
commit | 6ef7da0197735a16aa534e9e2c80709d3d6e8c56 (patch) | |
tree | f4ecf00513f7e55c9e44e819d6c336191fb38ee2 /lib/CodeGen/InterferenceCache.h | |
parent | 3bf7a1cc3c090e766b8912c6a14c3e2ec5dde7f8 (diff) | |
download | llvm-6ef7da0197735a16aa534e9e2c80709d3d6e8c56.tar.gz llvm-6ef7da0197735a16aa534e9e2c80709d3d6e8c56.tar.bz2 llvm-6ef7da0197735a16aa534e9e2c80709d3d6e8c56.tar.xz |
Add register mask support to InterferenceCache.
This makes global live range splitting behave identically with and
without register mask operands.
This is not necessarily the best way of using register masks for live
range splitting. It would be more efficient to first split global live
ranges around calls (i.e., register masks), and reserve the fine grained
per-physreg interference guidance for global live ranges that do not
cross calls.
For now the goal is to produce identical assembly when enabling register
masks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150259 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/InterferenceCache.h')
-rw-r--r-- | lib/CodeGen/InterferenceCache.h | 12 |
1 files changed, 9 insertions, 3 deletions
diff --git a/lib/CodeGen/InterferenceCache.h b/lib/CodeGen/InterferenceCache.h index 437f9848b0..485a325aa1 100644 --- a/lib/CodeGen/InterferenceCache.h +++ b/lib/CodeGen/InterferenceCache.h @@ -18,6 +18,8 @@ namespace llvm { +class LiveIntervals; + class InterferenceCache { const TargetRegisterInfo *TRI; LiveIntervalUnion *LIUArray; @@ -51,6 +53,9 @@ class InterferenceCache { /// Indexes - Mapping block numbers to SlotIndex ranges. SlotIndexes *Indexes; + /// LIS - Used for accessing register mask interference maps. + LiveIntervals *LIS; + /// PrevPos - The previous position the iterators were moved to. SlotIndex PrevPos; @@ -70,13 +75,14 @@ class InterferenceCache { void update(unsigned MBBNum); public: - Entry() : PhysReg(0), Tag(0), RefCount(0), Indexes(0) {} + Entry() : PhysReg(0), Tag(0), RefCount(0), Indexes(0), LIS(0) {} - void clear(MachineFunction *mf, SlotIndexes *indexes) { + void clear(MachineFunction *mf, SlotIndexes *indexes, LiveIntervals *lis) { assert(!hasRefs() && "Cannot clear cache entry with references"); PhysReg = 0; MF = mf; Indexes = indexes; + LIS = lis; } unsigned getPhysReg() const { return PhysReg; } @@ -126,7 +132,7 @@ public: InterferenceCache() : TRI(0), LIUArray(0), MF(0), RoundRobin(0) {} /// init - Prepare cache for a new function. - void init(MachineFunction*, LiveIntervalUnion*, SlotIndexes*, + void init(MachineFunction*, LiveIntervalUnion*, SlotIndexes*, LiveIntervals*, const TargetRegisterInfo *); /// getMaxCursors - Return the maximum number of concurrent cursors that can |