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| author | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2010-10-06 23:54:39 +0000 |
|---|---|---|
| committer | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2010-10-06 23:54:39 +0000 |
| commit | bf4699c56100a0184bbe4fb53937c7204ca1ceb0 (patch) | |
| tree | 71539b0c1c119eca32aa95dcbf80949f41355875 /lib/CodeGen/MachineCSE.cpp | |
| parent | 893ab5d7014dd112fb111a67504bd556be9bd393 (diff) | |
| download | llvm-bf4699c56100a0184bbe4fb53937c7204ca1ceb0.tar.gz llvm-bf4699c56100a0184bbe4fb53937c7204ca1ceb0.tar.bz2 llvm-bf4699c56100a0184bbe4fb53937c7204ca1ceb0.tar.xz | |
Add MachineRegisterInfo::constrainRegClass and use it in MachineCSE.
This function is intended to be used when inserting a machine instruction that
trivially restricts the legal registers, like LEA requiring a GR32_NOSP
argument.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115875 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/MachineCSE.cpp')
| -rw-r--r-- | lib/CodeGen/MachineCSE.cpp | 9 |
1 files changed, 2 insertions, 7 deletions
diff --git a/lib/CodeGen/MachineCSE.cpp b/lib/CodeGen/MachineCSE.cpp index 272b54dea1..9d09f608ee 100644 --- a/lib/CodeGen/MachineCSE.cpp +++ b/lib/CodeGen/MachineCSE.cpp @@ -120,17 +120,12 @@ bool MachineCSE::PerformTrivialCoalescing(MachineInstr *MI, continue; if (DefMI->getOperand(0).getSubReg() || DefMI->getOperand(1).getSubReg()) continue; - const TargetRegisterClass *SRC = MRI->getRegClass(SrcReg); - const TargetRegisterClass *RC = MRI->getRegClass(Reg); - const TargetRegisterClass *NewRC = getCommonSubClass(RC, SRC); - if (!NewRC) + if (!MRI->constrainRegClass(SrcReg, MRI->getRegClass(Reg))) continue; DEBUG(dbgs() << "Coalescing: " << *DefMI); - DEBUG(dbgs() << "*** to: " << *MI); + DEBUG(dbgs() << "*** to: " << *MI); MO.setReg(SrcReg); MRI->clearKillFlags(SrcReg); - if (NewRC != SRC) - MRI->setRegClass(SrcReg, NewRC); DefMI->eraseFromParent(); ++NumCoalesces; Changed = true; |