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authorEvan Cheng <evan.cheng@apple.com>2010-03-08 23:28:08 +0000
committerEvan Cheng <evan.cheng@apple.com>2010-03-08 23:28:08 +0000
commit6c3b8ac6c9dfd7687a8097586925c09a84ab3d2e (patch)
treed5568a878947eb99d62f40df41d2506d0a912793 /lib/CodeGen/MachineCSE.cpp
parent57578766aa33d1a22cd124316df318db3e44f34a (diff)
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Restrict machine cse to really trivial coalescing. Leave the heavy lifting to a real coalescer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98007 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/MachineCSE.cpp')
-rw-r--r--lib/CodeGen/MachineCSE.cpp3
1 files changed, 3 insertions, 0 deletions
diff --git a/lib/CodeGen/MachineCSE.cpp b/lib/CodeGen/MachineCSE.cpp
index b376e3d05f..ce8ebbc601 100644
--- a/lib/CodeGen/MachineCSE.cpp
+++ b/lib/CodeGen/MachineCSE.cpp
@@ -91,7 +91,10 @@ bool MachineCSE::PerformTrivialCoalescing(MachineInstr *MI,
unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
if (TII->isMoveInstr(*DefMI, SrcReg, DstReg, SrcSubIdx, DstSubIdx) &&
TargetRegisterInfo::isVirtualRegister(SrcReg) &&
+ MRI->getRegClass(SrcReg) == MRI->getRegClass(Reg) &&
!SrcSubIdx && !DstSubIdx) {
+ DEBUG(dbgs() << "Coalescing: " << *DefMI);
+ DEBUG(dbgs() << "*** to: " << *MI);
MO.setReg(SrcReg);
DefMI->eraseFromParent();
++NumCoalesces;