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| author | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2012-07-04 23:53:23 +0000 |
|---|---|---|
| committer | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2012-07-04 23:53:23 +0000 |
| commit | 33a537a5c41e60507ac9a4ea987c1a395cbb74fe (patch) | |
| tree | d21a9d1bc22c8eb657ea1607bd5cb9ccc2907119 /lib/CodeGen/MachineInstr.cpp | |
| parent | 9389ec7375eb184ad017b7a1f09600cc4c2be4cd (diff) | |
| download | llvm-33a537a5c41e60507ac9a4ea987c1a395cbb74fe.tar.gz llvm-33a537a5c41e60507ac9a4ea987c1a395cbb74fe.tar.bz2 llvm-33a537a5c41e60507ac9a4ea987c1a395cbb74fe.tar.xz | |
Allow trailing physreg RegisterSDNode operands on non-variadic instructions.
Also allow trailing register mask operands on non-variadic both
MachineSDNodes and MachineInstrs.
The extra physreg RegisterSDNode operands are added to the MI as
<imp-use> operands. This makes it possible to have non-variadic call
instructions.
Call and return instructions really are non-variadic, the argument
registers should only be used implicitly - they are not part of the
encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159727 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/MachineInstr.cpp')
| -rw-r--r-- | lib/CodeGen/MachineInstr.cpp | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/lib/CodeGen/MachineInstr.cpp b/lib/CodeGen/MachineInstr.cpp index 5d16c20460..85b5e39864 100644 --- a/lib/CodeGen/MachineInstr.cpp +++ b/lib/CodeGen/MachineInstr.cpp @@ -660,7 +660,9 @@ void MachineInstr::addOperand(const MachineOperand &Op) { // OpNo now points as the desired insertion point. Unless this is a variadic // instruction, only implicit regs are allowed beyond MCID->getNumOperands(). - assert((isImpReg || MCID->isVariadic() || OpNo < MCID->getNumOperands()) && + // RegMask operands go between the explicit and implicit operands. + assert((isImpReg || Op.isRegMask() || MCID->isVariadic() || + OpNo < MCID->getNumOperands()) && "Trying to add an operand to a machine instr that is already done!"); // All operands from OpNo have been removed from RegInfo. If the Operands |