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authorJakob Stoklund Olesen <stoklund@2pi.dk>2012-12-20 22:54:05 +0000
committerJakob Stoklund Olesen <stoklund@2pi.dk>2012-12-20 22:54:05 +0000
commit56706db45bbc7be0c087451ca9f1d258324df4b2 (patch)
tree9d3f00f5794af62b0a2abd3af64b29f07771e19b /lib/CodeGen/MachineInstr.cpp
parentbe06aacaa9a270384599bbfa850b967e9996b9fb (diff)
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Require the two-argument MI::addOperand(MF, MO) for dangling instructions.
Instructions that are inserted in a basic block can still be decorated with addOperand(MO). Make the two-argument addOperand() function contain the actual implementation. This function will now always have a valid MF reference that it can use for memory allocation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170798 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/MachineInstr.cpp')
-rw-r--r--lib/CodeGen/MachineInstr.cpp10
1 files changed, 9 insertions, 1 deletions
diff --git a/lib/CodeGen/MachineInstr.cpp b/lib/CodeGen/MachineInstr.cpp
index a98949025a..675df1933f 100644
--- a/lib/CodeGen/MachineInstr.cpp
+++ b/lib/CodeGen/MachineInstr.cpp
@@ -603,11 +603,19 @@ void MachineInstr::AddRegOperandsToUseLists(MachineRegisterInfo &MRI) {
MRI.addRegOperandToUseList(&Operands[i]);
}
+void MachineInstr::addOperand(const MachineOperand &Op) {
+ MachineBasicBlock *MBB = getParent();
+ assert(MBB && "Use MachineInstrBuilder to add operands to dangling instrs");
+ MachineFunction *MF = MBB->getParent();
+ assert(MF && "Use MachineInstrBuilder to add operands to dangling instrs");
+ addOperand(*MF, Op);
+}
+
/// addOperand - Add the specified operand to the instruction. If it is an
/// implicit operand, it is added to the end of the operand list. If it is
/// an explicit operand it is added at the end of the explicit operand list
/// (before the first implicit operand).
-void MachineInstr::addOperand(const MachineOperand &Op) {
+void MachineInstr::addOperand(MachineFunction &MF, const MachineOperand &Op) {
assert(MCID && "Cannot add operands before providing an instr descriptor");
bool isImpReg = Op.isReg() && Op.isImplicit();
MachineRegisterInfo *RegInfo = getRegInfo();