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authorEvan Cheng <evan.cheng@apple.com>2009-06-14 20:22:55 +0000
committerEvan Cheng <evan.cheng@apple.com>2009-06-14 20:22:55 +0000
commit90f95f88c6ce09c6744777dc9d140c3c77203b92 (patch)
tree3996a490bf685eea1de9b1579d28f69500dbf8a6 /lib/CodeGen/MachineRegisterInfo.cpp
parentcaf6b2bbaf40580596e974b5eee0a7e59b58bd98 (diff)
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Move register allocation preference (or hint) from LiveInterval to MachineRegisterInfo. This allows more passes to set them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73346 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/MachineRegisterInfo.cpp')
-rw-r--r--lib/CodeGen/MachineRegisterInfo.cpp2
1 files changed, 2 insertions, 0 deletions
diff --git a/lib/CodeGen/MachineRegisterInfo.cpp b/lib/CodeGen/MachineRegisterInfo.cpp
index 4f5ab1f586..9649c4c44c 100644
--- a/lib/CodeGen/MachineRegisterInfo.cpp
+++ b/lib/CodeGen/MachineRegisterInfo.cpp
@@ -16,6 +16,7 @@ using namespace llvm;
MachineRegisterInfo::MachineRegisterInfo(const TargetRegisterInfo &TRI) {
VRegInfo.reserve(256);
+ RegAllocHints.reserve(256);
RegClass2VRegMap.resize(TRI.getNumRegClasses()+1); // RC ID starts at 1.
UsedPhysRegs.resize(TRI.getNumRegs());
@@ -64,6 +65,7 @@ MachineRegisterInfo::createVirtualRegister(const TargetRegisterClass *RegClass){
// Add a reg, but keep track of whether the vector reallocated or not.
void *ArrayBase = VRegInfo.empty() ? 0 : &VRegInfo[0];
VRegInfo.push_back(std::make_pair(RegClass, (MachineOperand*)0));
+ RegAllocHints.push_back(std::make_pair(RA_None, 0));
if (!((&VRegInfo[0] == ArrayBase || VRegInfo.size() == 1)))
// The vector reallocated, handle this now.