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author | Patrik Hägglund <patrik.h.hagglund@ericsson.com> | 2012-05-23 12:12:58 +0000 |
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committer | Patrik Hägglund <patrik.h.hagglund@ericsson.com> | 2012-05-23 12:12:58 +0000 |
commit | d76938788b4b682043a74befbb6320ce0077ddc9 (patch) | |
tree | c2ef0e924a60a1df08a17712608038aa981c41c2 /lib/CodeGen/RegAllocPBQP.cpp | |
parent | 06fdbaa9145f01a291d4981ca5120b7bdcad44c6 (diff) | |
download | llvm-d76938788b4b682043a74befbb6320ce0077ddc9.tar.gz llvm-d76938788b4b682043a74befbb6320ce0077ddc9.tar.bz2 llvm-d76938788b4b682043a74befbb6320ce0077ddc9.tar.xz |
Small fix for the debug output from PBQP (PR12822).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157319 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/RegAllocPBQP.cpp')
-rw-r--r-- | lib/CodeGen/RegAllocPBQP.cpp | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/lib/CodeGen/RegAllocPBQP.cpp b/lib/CodeGen/RegAllocPBQP.cpp index 56c7241ef1..cfdfa59d6d 100644 --- a/lib/CodeGen/RegAllocPBQP.cpp +++ b/lib/CodeGen/RegAllocPBQP.cpp @@ -544,7 +544,8 @@ bool RegAllocPBQP::mapPBQPToRegAlloc(const PBQPRAProblem &problem, if (problem.isPRegOption(vreg, alloc)) { unsigned preg = problem.getPRegForOption(vreg, alloc); - DEBUG(dbgs() << "VREG " << vreg << " -> " << tri->getName(preg) << "\n"); + DEBUG(dbgs() << "VREG " << PrintReg(vreg, tri) << " -> " + << tri->getName(preg) << "\n"); assert(preg != 0 && "Invalid preg selected."); vrm->assignVirt2Phys(vreg, preg); } else if (problem.isSpillOption(vreg, alloc)) { @@ -553,7 +554,7 @@ bool RegAllocPBQP::mapPBQPToRegAlloc(const PBQPRAProblem &problem, LiveRangeEdit LRE(&lis->getInterval(vreg), newSpills, *mf, *lis, vrm); spiller->spill(LRE); - DEBUG(dbgs() << "VREG " << vreg << " -> SPILLED (Cost: " + DEBUG(dbgs() << "VREG " << PrintReg(vreg, tri) << " -> SPILLED (Cost: " << LRE.getParent().weight << ", New vregs: "); // Copy any newly inserted live intervals into the list of regs to @@ -561,7 +562,7 @@ bool RegAllocPBQP::mapPBQPToRegAlloc(const PBQPRAProblem &problem, for (LiveRangeEdit::iterator itr = LRE.begin(), end = LRE.end(); itr != end; ++itr) { assert(!(*itr)->empty() && "Empty spill range."); - DEBUG(dbgs() << (*itr)->reg << " "); + DEBUG(dbgs() << PrintReg((*itr)->reg, tri) << " "); vregsToAlloc.insert((*itr)->reg); } |