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author | Evan Cheng <evan.cheng@apple.com> | 2010-06-16 07:35:02 +0000 |
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committer | Evan Cheng <evan.cheng@apple.com> | 2010-06-16 07:35:02 +0000 |
commit | 46df4eb46e784036cf895db271fe29e1cf2a975a (patch) | |
tree | 7a7225e258b7af507f92aec209f538b3bcf78671 /lib/CodeGen/RegisterScavenging.cpp | |
parent | ffd33cd36494cf29a0b0c80f00ed1a51b599b31f (diff) | |
download | llvm-46df4eb46e784036cf895db271fe29e1cf2a975a.tar.gz llvm-46df4eb46e784036cf895db271fe29e1cf2a975a.tar.bz2 llvm-46df4eb46e784036cf895db271fe29e1cf2a975a.tar.xz |
Make post-ra scheduling, anti-dep breaking, and register scavenger (conservatively) aware of predicated instructions. This enables ARM to move if-conversion before post-ra scheduler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106091 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/RegisterScavenging.cpp')
-rw-r--r-- | lib/CodeGen/RegisterScavenging.cpp | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/lib/CodeGen/RegisterScavenging.cpp b/lib/CodeGen/RegisterScavenging.cpp index b3e79756b6..3eefedadf2 100644 --- a/lib/CodeGen/RegisterScavenging.cpp +++ b/lib/CodeGen/RegisterScavenging.cpp @@ -141,6 +141,10 @@ void RegScavenger::forward() { // Find out which registers are early clobbered, killed, defined, and marked // def-dead in this instruction. + // FIXME: The scavenger is not predication aware. If the instruction is + // predicated, conservatively assume "kill" markers do not actually kill the + // register. Similarly ignores "dead" markers. + bool isPred = TII->isPredicated(MI); BitVector EarlyClobberRegs(NumPhysRegs); BitVector KillRegs(NumPhysRegs); BitVector DefRegs(NumPhysRegs); @@ -155,11 +159,11 @@ void RegScavenger::forward() { if (MO.isUse()) { // Two-address operands implicitly kill. - if (MO.isKill() || MI->isRegTiedToDefOperand(i)) + if (!isPred && (MO.isKill() || MI->isRegTiedToDefOperand(i))) addRegWithSubRegs(KillRegs, Reg); } else { assert(MO.isDef()); - if (MO.isDead()) + if (!isPred && MO.isDead()) addRegWithSubRegs(DeadRegs, Reg); else addRegWithSubRegs(DefRegs, Reg); |