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authorAndrew Trick <atrick@apple.com>2012-04-13 23:29:54 +0000
committerAndrew Trick <atrick@apple.com>2012-04-13 23:29:54 +0000
commit007079201276368736fc893d4d5ec7aeeca00823 (patch)
treea10f76b12b2b8554c51151d7f62d7b7781a61afc /lib/CodeGen/ScheduleDAGInstrs.cpp
parent6335e41d38ff85c263451c5cd71b2588c5cc74cc (diff)
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misched: Added CanHandleTerminators.
This is a special flag for targets that really want their block terminators in the DAG. The default scheduler cannot handle this correctly, so it becomes the specialized scheduler's responsibility to schedule terminators. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154712 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/ScheduleDAGInstrs.cpp')
-rw-r--r--lib/CodeGen/ScheduleDAGInstrs.cpp6
1 files changed, 3 insertions, 3 deletions
diff --git a/lib/CodeGen/ScheduleDAGInstrs.cpp b/lib/CodeGen/ScheduleDAGInstrs.cpp
index 6be1ab7f5b..d46eb896e5 100644
--- a/lib/CodeGen/ScheduleDAGInstrs.cpp
+++ b/lib/CodeGen/ScheduleDAGInstrs.cpp
@@ -39,8 +39,8 @@ ScheduleDAGInstrs::ScheduleDAGInstrs(MachineFunction &mf,
LiveIntervals *lis)
: ScheduleDAG(mf), MLI(mli), MDT(mdt), MFI(mf.getFrameInfo()),
InstrItins(mf.getTarget().getInstrItineraryData()), LIS(lis),
- IsPostRA(IsPostRAFlag), UnitLatencies(false), LoopRegs(MLI, MDT),
- FirstDbgValue(0) {
+ IsPostRA(IsPostRAFlag), UnitLatencies(false), CanHandleTerminators(false),
+ LoopRegs(MLI, MDT), FirstDbgValue(0) {
assert((IsPostRA || LIS) && "PreRA scheduling requires LiveIntervals");
DbgValues.clear();
assert(!(IsPostRA && MRI.getNumVirtRegs()) &&
@@ -554,7 +554,7 @@ void ScheduleDAGInstrs::buildSchedGraph(AliasAnalysis *AA) {
continue;
}
- assert(!MI->isTerminator() && !MI->isLabel() &&
+ assert((!MI->isTerminator() || CanHandleTerminators) && !MI->isLabel() &&
"Cannot schedule terminators or labels!");
SUnit *SU = MISUnitMap[MI];