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| author | Andrew Trick <atrick@apple.com> | 2012-02-21 04:51:23 +0000 |
|---|---|---|
| committer | Andrew Trick <atrick@apple.com> | 2012-02-21 04:51:23 +0000 |
| commit | 19273aec441411b4d571fdb87c6daa0fbe7a33a0 (patch) | |
| tree | ea01b1d19560a814c4686c3edebacac5b9e40f06 /lib/CodeGen/ScheduleDAGInstrs.cpp | |
| parent | e8ccb049136506cb71b84a55000bad3c1440ee7c (diff) | |
| download | llvm-19273aec441411b4d571fdb87c6daa0fbe7a33a0.tar.gz llvm-19273aec441411b4d571fdb87c6daa0fbe7a33a0.tar.bz2 llvm-19273aec441411b4d571fdb87c6daa0fbe7a33a0.tar.xz | |
Clear virtual registers after they are no longer referenced.
Passes after RegAlloc should be able to rely on MRI->getNumVirtRegs() == 0.
This makes sharing code for pre/postRA passes more robust.
Now, to check if a pass is running before the RA pipeline begins, use MRI->isSSA().
To check if a pass is running after the RA pipeline ends, use !MRI->getNumVirtRegs().
PEI resets virtual regs when it's done scavenging.
PTX will either have to provide its own PEI pass or assign physregs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151032 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/ScheduleDAGInstrs.cpp')
| -rw-r--r-- | lib/CodeGen/ScheduleDAGInstrs.cpp | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/lib/CodeGen/ScheduleDAGInstrs.cpp b/lib/CodeGen/ScheduleDAGInstrs.cpp index b3349209a5..879b65f9d0 100644 --- a/lib/CodeGen/ScheduleDAGInstrs.cpp +++ b/lib/CodeGen/ScheduleDAGInstrs.cpp @@ -40,6 +40,8 @@ ScheduleDAGInstrs::ScheduleDAGInstrs(MachineFunction &mf, UnitLatencies(false), Defs(TRI->getNumRegs()), Uses(TRI->getNumRegs()), LoopRegs(MLI, MDT), FirstDbgValue(0) { DbgValues.clear(); + assert(!(IsPostRA && MF.getRegInfo().getNumVirtRegs()) && + "Virtual registers must be removed prior to PostRA scheduling"); } /// Run - perform scheduling. |