diff options
author | Evan Cheng <evan.cheng@apple.com> | 2012-01-07 03:02:36 +0000 |
---|---|---|
committer | Evan Cheng <evan.cheng@apple.com> | 2012-01-07 03:02:36 +0000 |
commit | 977679d6034791fd48a344e5b990503ba50fc242 (patch) | |
tree | a53e7c18e92d71fe32a7df3f76f4231433bc08eb /lib/CodeGen/ScheduleDAGInstrs.cpp | |
parent | ccec74738d0fc34f4bc2ac6909324e62705f1c38 (diff) | |
download | llvm-977679d6034791fd48a344e5b990503ba50fc242.tar.gz llvm-977679d6034791fd48a344e5b990503ba50fc242.tar.bz2 llvm-977679d6034791fd48a344e5b990503ba50fc242.tar.xz |
Added a late machine instruction copy propagation pass. This catches
opportunities that only present themselves after late optimizations
such as tail duplication .e.g.
## BB#1:
movl %eax, %ecx
movl %ecx, %eax
ret
The register allocator also leaves some of them around (due to false
dep between copies from phi-elimination, etc.)
This required some changes in codegen passes. Post-ra scheduler and the
pseudo-instruction expansion passes have been moved after branch folding
and tail merging. They were before branch folding before because it did
not always update block livein's. That's fixed now. The pass change makes
independently since we want to properly schedule instructions after
branch folding / tail duplication.
rdar://10428165
rdar://10640363
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147716 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/ScheduleDAGInstrs.cpp')
-rw-r--r-- | lib/CodeGen/ScheduleDAGInstrs.cpp | 7 |
1 files changed, 1 insertions, 6 deletions
diff --git a/lib/CodeGen/ScheduleDAGInstrs.cpp b/lib/CodeGen/ScheduleDAGInstrs.cpp index b02f3b6e1e..a6556a51c8 100644 --- a/lib/CodeGen/ScheduleDAGInstrs.cpp +++ b/lib/CodeGen/ScheduleDAGInstrs.cpp @@ -136,13 +136,8 @@ static const Value *getUnderlyingObjectForInstr(const MachineInstr *MI, void ScheduleDAGInstrs::StartBlock(MachineBasicBlock *BB) { LoopRegs.Deps.clear(); if (MachineLoop *ML = MLI.getLoopFor(BB)) - if (BB == ML->getLoopLatch()) { - MachineBasicBlock *Header = ML->getHeader(); - for (MachineBasicBlock::livein_iterator I = Header->livein_begin(), - E = Header->livein_end(); I != E; ++I) - LoopLiveInRegs.insert(*I); + if (BB == ML->getLoopLatch()) LoopRegs.VisitLoop(ML); - } } /// AddSchedBarrierDeps - Add dependencies from instructions in the current |