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| author | Craig Topper <craig.topper@gmail.com> | 2012-03-04 10:43:23 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@gmail.com> | 2012-03-04 10:43:23 +0000 |
| commit | e4fd907e72a599eddfa7a81eac4366b5b82523e3 (patch) | |
| tree | e5a97f58db2537457943547ba007ee63299ae555 /lib/CodeGen/ScheduleDAGInstrs.cpp | |
| parent | 9406da6e664a24c8e408cbba63daf162ca166ed9 (diff) | |
| download | llvm-e4fd907e72a599eddfa7a81eac4366b5b82523e3.tar.gz llvm-e4fd907e72a599eddfa7a81eac4366b5b82523e3.tar.bz2 llvm-e4fd907e72a599eddfa7a81eac4366b5b82523e3.tar.xz | |
Use uint16_t to store register overlaps to reduce static data.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152001 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/ScheduleDAGInstrs.cpp')
| -rw-r--r-- | lib/CodeGen/ScheduleDAGInstrs.cpp | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/lib/CodeGen/ScheduleDAGInstrs.cpp b/lib/CodeGen/ScheduleDAGInstrs.cpp index 8f9d85b695..c0ccdb33e8 100644 --- a/lib/CodeGen/ScheduleDAGInstrs.cpp +++ b/lib/CodeGen/ScheduleDAGInstrs.cpp @@ -215,7 +215,7 @@ void ScheduleDAGInstrs::addPhysRegDataDeps(SUnit *SU, unsigned SpecialAddressLatency = ST.getSpecialAddressLatency(); unsigned DataLatency = SU->Latency; - for (const unsigned *Alias = TRI->getOverlaps(MO.getReg()); *Alias; ++Alias) { + for (const uint16_t *Alias = TRI->getOverlaps(MO.getReg()); *Alias; ++Alias) { if (!Uses.contains(*Alias)) continue; std::vector<SUnit*> &UseList = Uses[*Alias]; @@ -268,7 +268,7 @@ void ScheduleDAGInstrs::addPhysRegDeps(SUnit *SU, unsigned OperIdx) { // TODO: Using a latency of 1 here for output dependencies assumes // there's no cost for reusing registers. SDep::Kind Kind = MO.isUse() ? SDep::Anti : SDep::Output; - for (const unsigned *Alias = TRI->getOverlaps(MO.getReg()); *Alias; ++Alias) { + for (const uint16_t *Alias = TRI->getOverlaps(MO.getReg()); *Alias; ++Alias) { if (!Defs.contains(*Alias)) continue; std::vector<SUnit *> &DefList = Defs[*Alias]; |