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| author | Patrik Hagglund <patrik.h.hagglund@ericsson.com> | 2012-12-11 11:14:33 +0000 |
|---|---|---|
| committer | Patrik Hagglund <patrik.h.hagglund@ericsson.com> | 2012-12-11 11:14:33 +0000 |
| commit | 34525f9ac098c1c6bc9002886d6da3039a284fd2 (patch) | |
| tree | b4cb498a55dda76f1a134df25d3c587cc35b2f83 /lib/CodeGen/SelectionDAG/DAGCombiner.cpp | |
| parent | 7550f96b2f3a5e187f737ddad45563962fbd509c (diff) | |
| download | llvm-34525f9ac098c1c6bc9002886d6da3039a284fd2.tar.gz llvm-34525f9ac098c1c6bc9002886d6da3039a284fd2.tar.bz2 llvm-34525f9ac098c1c6bc9002886d6da3039a284fd2.tar.xz | |
Revert EVT->MVT changes, r169836-169851, due to buildbot failures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169854 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/SelectionDAG/DAGCombiner.cpp')
| -rw-r--r-- | lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 9 |
1 files changed, 3 insertions, 6 deletions
diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index 3b8b2371db..1c28d6dcaf 100644 --- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -2632,8 +2632,7 @@ SDValue DAGCombiner::visitAND(SDNode *N) { bool isInteger = LL.getValueType().isInteger(); ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger); if (Result != ISD::SETCC_INVALID && - (!LegalOperations || - TLI.isCondCodeLegal(Result, LL.getSimpleValueType()))) + (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType()))) return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(), LL, LR, Result); } @@ -3141,8 +3140,7 @@ SDValue DAGCombiner::visitOR(SDNode *N) { bool isInteger = LL.getValueType().isInteger(); ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger); if (Result != ISD::SETCC_INVALID && - (!LegalOperations || - TLI.isCondCodeLegal(Result, LL.getSimpleValueType()))) + (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType()))) return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(), LL, LR, Result); } @@ -3405,8 +3403,7 @@ SDValue DAGCombiner::visitXOR(SDNode *N) { ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(), isInt); - if (!LegalOperations || - TLI.isCondCodeLegal(NotCC, LHS.getSimpleValueType())) { + if (!LegalOperations || TLI.isCondCodeLegal(NotCC, LHS.getValueType())) { switch (N0.getOpcode()) { default: llvm_unreachable("Unhandled SetCC Equivalent!"); |