Fix PR7162: Use source register classes and sub-indices to determine the correct register class of the definitions of REG_SEQUENCE.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104050 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 6 insertions, 4 deletions

diff --git a/lib/CodeGen/SelectionDAG/InstrEmitter.cpp b/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
index 16bd40ca65..2f8f255b5b 100644
--- a/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
+++ b/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
@@ -545,16 +545,18 @@ void InstrEmitter::EmitRegSequence(SDNode *Node,
   const TargetInstrDesc &II = TII->get(TargetOpcode::REG_SEQUENCE);
   for (unsigned i = 0; i != NumOps; ++i) {
     SDValue Op = Node->getOperand(i);
-#ifndef NDEBUG
     if (i & 1) {
       unsigned SubIdx = cast<ConstantSDNode>(Op)->getZExtValue();
       unsigned SubReg = getVR(Node->getOperand(i-1), VRBaseMap);
       const TargetRegisterClass *TRC = MRI->getRegClass(SubReg);
       const TargetRegisterClass *SRC =
-        getSuperRegisterRegClass(TRC, SubIdx, Node->getValueType(0));
-      assert(SRC == RC && "Invalid subregister index in REG_SEQUENCE");
+        TRI->getMatchingSuperRegClass(RC, TRC, SubIdx);
+      //getSuperRegisterRegClass(TRC, SubIdx, Node->getValueType(0));
+      if (!SRC)
+        llvm_unreachable("Invalid subregister index in REG_SEQUENCE");
+      if (SRC != RC)
+        MRI->setRegClass(NewVReg, SRC);
     }
-#endif
     AddOperand(MI, Op, i+1, &II, VRBaseMap, /*IsDebug=*/false,
                IsClone, IsCloned);
   }