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| author | Nadav Rotem <nadav.rotem@intel.com> | 2012-04-15 15:08:09 +0000 |
|---|---|---|
| committer | Nadav Rotem <nadav.rotem@intel.com> | 2012-04-15 15:08:09 +0000 |
| commit | 3ab32ea49ec13182f1397dc89c37551692f67140 (patch) | |
| tree | 977dde5f8d6f1fea880e55175174f2a5a06e282d /lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp | |
| parent | 73c504af9d86a426532ee32c5d07a4b872794675 (diff) | |
| download | llvm-3ab32ea49ec13182f1397dc89c37551692f67140.tar.gz llvm-3ab32ea49ec13182f1397dc89c37551692f67140.tar.bz2 llvm-3ab32ea49ec13182f1397dc89c37551692f67140.tar.xz | |
When emulating vselect using OR/AND/XOR make sure to bitcast the result back to the original type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154764 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp')
| -rw-r--r-- | lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp b/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp index 3ae8345bd1..9fe4480d11 100644 --- a/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp +++ b/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp @@ -417,7 +417,8 @@ SDValue VectorLegalizer::ExpandVSELECT(SDValue Op) { Op1 = DAG.getNode(ISD::AND, DL, VT, Op1, Mask); Op2 = DAG.getNode(ISD::AND, DL, VT, Op2, NotMask); - return DAG.getNode(ISD::OR, DL, VT, Op1, Op2); + SDValue Val = DAG.getNode(ISD::OR, DL, VT, Op1, Op2); + return DAG.getNode(ISD::BITCAST, DL, Op.getValueType(), Val); } SDValue VectorLegalizer::ExpandUINT_TO_FLOAT(SDValue Op) { |