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authorNadav Rotem <nadav.rotem@intel.com>2011-09-18 10:29:29 +0000
committerNadav Rotem <nadav.rotem@intel.com>2011-09-18 10:29:29 +0000
commitb6266fb6026bdd900d8f045bf01300ef549e1802 (patch)
treeab826de152890bb3f5b2ecdf033a567671434b07 /lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
parent89af15ee11b0cab2315fe2affa54189619aac8e7 (diff)
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white space cleanups
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139994 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp')
-rw-r--r--lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp9
1 files changed, 4 insertions, 5 deletions
diff --git a/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp b/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
index 7c59c7eb5a..80b4c6053a 100644
--- a/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
+++ b/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
@@ -61,8 +61,8 @@ class VectorLegalizer {
// Implements expansion for UINT_TO_FLOAT; falls back to UnrollVectorOp if
// SINT_TO_FLOAT and SHR on vectors isn't legal.
SDValue ExpandUINT_TO_FLOAT(SDValue Op);
- // Implement vselect in terms of XOR, AND,OR when blend is not supported
- // by the target.
+ // Implement vselect in terms of XOR, AND, OR when blend is not supported
+ // by the target.
SDValue ExpandVSELECT(SDValue Op);
SDValue ExpandFNEG(SDValue Op);
// Implements vector promotion; this is essentially just bitcasting the
@@ -277,9 +277,8 @@ SDValue VectorLegalizer::ExpandVSELECT(SDValue Op) {
// AND,OR,XOR, we will have to scalarize the op.
if (!TLI.isOperationLegalOrCustom(ISD::AND, VT) ||
!TLI.isOperationLegalOrCustom(ISD::XOR, VT) ||
- !TLI.isOperationLegalOrCustom(ISD::OR, VT)) {
- return DAG.UnrollVectorOp(Op.getNode());
- }
+ !TLI.isOperationLegalOrCustom(ISD::OR, VT))
+ return DAG.UnrollVectorOp(Op.getNode());
assert(VT.getSizeInBits() == OVT.getSizeInBits() && "Invalid mask size");
// Bitcast the operands to be the same type as the mask.