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| author | Nadav Rotem <nadav.rotem@intel.com> | 2012-01-03 22:12:28 +0000 |
|---|---|---|
| committer | Nadav Rotem <nadav.rotem@intel.com> | 2012-01-03 22:12:28 +0000 |
| commit | 316477dd543b5ae30b832ed4c7708f7aaa51747c (patch) | |
| tree | 93d71834cc15ecc4429742eaee50817be930be9b /lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp | |
| parent | 3d1161e9ae2aedc45f40cc1b7be1db3df2094903 (diff) | |
| download | llvm-316477dd543b5ae30b832ed4c7708f7aaa51747c.tar.gz llvm-316477dd543b5ae30b832ed4c7708f7aaa51747c.tar.bz2 llvm-316477dd543b5ae30b832ed4c7708f7aaa51747c.tar.xz | |
Fix incorrect widening of the bitcast sdnode in case the incoming operand is integer-promoted.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147484 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp')
| -rw-r--r-- | lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp b/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp index 7ca0d1e5c0..6b267c311d 100644 --- a/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp +++ b/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp @@ -1571,6 +1571,12 @@ SDValue DAGTypeLegalizer::WidenVecRes_BITCAST(SDNode *N) { case TargetLowering::TypeLegal: break; case TargetLowering::TypePromoteInteger: + // If the incoming type is a vector that is being promoted, then + // we know that the elements are arranged differently and that we + // must perform the conversion using a stack slot. + if (InVT.isVector()) + break; + // If the InOp is promoted to the same size, convert it. Otherwise, // fall out of the switch and widen the promoted input. InOp = GetPromotedInteger(InOp); |