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| author | Christian Konig <christian.koenig@amd.com> | 2013-03-20 15:43:00 +0000 |
|---|---|---|
| committer | Christian Konig <christian.koenig@amd.com> | 2013-03-20 15:43:00 +0000 |
| commit | 61aba54f2c0f432179dfaa758bdb2bf1b9929814 (patch) | |
| tree | b0bf143c2378cba0fc49b72a990d45479f8254ac /lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp | |
| parent | fa963a885c074b3b0d6cc2466036297c476f7103 (diff) | |
| download | llvm-61aba54f2c0f432179dfaa758bdb2bf1b9929814.tar.gz llvm-61aba54f2c0f432179dfaa758bdb2bf1b9929814.tar.bz2 llvm-61aba54f2c0f432179dfaa758bdb2bf1b9929814.tar.xz | |
Revert "pre-RA-sched: fix TargetOpcode usage"
This reverts commit 06091513c283c863296f01cc7c2e86b56bb50d02.
The code is obviously wrong, but the trivial fix causes
inefficient code generation on X86. Somebody with more
knowledge of the code needs to take a look here.
Signed-off-by: Christian König <christian.koenig@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177529 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp')
| -rw-r--r-- | lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp | 30 |
1 files changed, 12 insertions, 18 deletions
diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp index 8d1b1021fe..c009cfcc51 100644 --- a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp +++ b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp @@ -1894,15 +1894,12 @@ unsigned RegReductionPQBase::getNodePriority(const SUnit *SU) const { // CopyToReg should be close to its uses to facilitate coalescing and // avoid spilling. return 0; - if (SU->getNode() && SU->getNode()->isMachineOpcode()) { - Opc = SU->getNode()->getMachineOpcode(); - if (Opc == TargetOpcode::EXTRACT_SUBREG || - Opc == TargetOpcode::SUBREG_TO_REG || - Opc == TargetOpcode::INSERT_SUBREG) - // EXTRACT_SUBREG, INSERT_SUBREG, and SUBREG_TO_REG nodes should be - // close to their uses to facilitate coalescing. - return 0; - } + if (Opc == TargetOpcode::EXTRACT_SUBREG || + Opc == TargetOpcode::SUBREG_TO_REG || + Opc == TargetOpcode::INSERT_SUBREG) + // EXTRACT_SUBREG, INSERT_SUBREG, and SUBREG_TO_REG nodes should be + // close to their uses to facilitate coalescing. + return 0; if (SU->NumSuccs == 0 && SU->NumPreds != 0) // If SU does not have a register use, i.e. it doesn't produce a value // that would be consumed (e.g. store), then it terminates a chain of @@ -2588,15 +2585,12 @@ static bool canEnableCoalescing(SUnit *SU) { // avoid spilling. return true; - if (SU->getNode() && SU->getNode()->isMachineOpcode()) { - Opc = SU->getNode()->getMachineOpcode(); - if (Opc == TargetOpcode::EXTRACT_SUBREG || - Opc == TargetOpcode::SUBREG_TO_REG || - Opc == TargetOpcode::INSERT_SUBREG) - // EXTRACT_SUBREG, INSERT_SUBREG, and SUBREG_TO_REG nodes should be - // close to their uses to facilitate coalescing. - return true; - } + if (Opc == TargetOpcode::EXTRACT_SUBREG || + Opc == TargetOpcode::SUBREG_TO_REG || + Opc == TargetOpcode::INSERT_SUBREG) + // EXTRACT_SUBREG, INSERT_SUBREG, and SUBREG_TO_REG nodes should be + // close to their uses to facilitate coalescing. + return true; if (SU->NumPreds == 0 && SU->NumSuccs != 0) // If SU does not have a register def, schedule it close to its uses |